Lecture – Interrupts

Hardware and Software interrupts
and event-driven programming

Ryan Robucci

Table of Contents

References

Reading from Book: Ch 7 Section 6

References and Resources

(Needs update, some links are stale)

What is an Interrupt?

Interrupt Overview

Interrupt Sources

Advantage Over Software Polling

Interrupt Servicing Flow

IDEXIF

IDEXPush PC to StackAlter PCClear Interrupt FlagInterrupt Flag?IF

Interrupt Vector Table

Event # Handler Address
0 funcPtr[0]
1 funcPtr[1]
2 funcPtr[2]
3 funcPtr[3]
4 funcPtr[4]
5 funcPtr[5]
... ...

Implementations of Interrupt Vector Table

  1. Vector holds jump to ISR
    .org WHERE_VECTORS_GO
    VEC0: jmp ISR0 ;jump to ISR
    VEC1: jmp ISR1 ;jump to ISR
    VEC2: jmp ISR2 ;jump to ISR
    
  2. Vector holds address of ISR
    .org WHERE_VECTORS_GO
    VEC0: ISR0 ;address of ISR
    VEC1: ISR1 ;address of ISR
    VEC2: ISR2 ;address of ISR
    

AVR Interrupt Vector Table

On AVR, interrupt vector table is implemented at the top of program memory with jmp instructions that are listed at beginning of program memory, position determines the interrupt number
Earlier (low-numbered) interrupts have higher priority

AVR mega169p Vector Addresses Example

Prog. Address jmp w/ Labels ;Code Comments
0x0000 jmp RESET ; Reset Handler
0x0002 jmp EXT_INT0 ; IRQ0 Handler
0x0004 jmp PCINT0 ; PCINT0 Handler
0x0006 jmp PCINT1 ; PCINT0 Handler
0x0008 jmp TIM2_COMP ; Timer2 Compare Handler
0x000A jmp TIM2_OVF ; Timer2 Overflow Handler
0x000C jmp TIM1_CAPT ; Timer1 Capture Handler
0x000E jmp TIM1_COMPA ; Timer1 CompareA Handler
0x0010 jmp TIM1_COMPB ; Timer1 CompareB Handler
0x0012 jmp TIM1_OVF ; Timer1 Overflow Handler
0x0014 jmp TIM0_COMP ; Timer0 Compare Handler
0x0016 jmp TIM0_OVF ; Timer0 Overflow Handler
0x0018 jmp SPI_STC ; SPI Transfer Complete Handler
0x001A jmp USART_RXCn ; USART0 RX Complete Handler
0x001C jmp USART_DRE ; USART0,UDRn Empty Handler
0x001E jmp USART_TXCn ; USART0 TX Complete Handler
0x0020 jmp USI_STRT ; USI Start Condition Handler
0x0022 jmp USI_OVFL ; USI Overflow Handler
0x0024 jmp ANA_COMP ; Analog Comparator Handler
0x0026 jmp ADC ; ADC Conversion Complete Handler
0x0028 jmp EE_RDY ; EEPROM Ready Handler
0x002A jmp SPM_RDY ; SPM Ready Handler
0x002C jmp LCD_SOF ; LCD Start of Frame Handler
;...
0x002E RESET: ldi r16, high(RAMEND); Main program start
0x002F out SPH,r16 Set Stack Pointer to top of RAM
0x0030 ldi r16, low(RAMEND)
. And so on...

Coding Interrupts in AVR Assembly

http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=89843

If using interrupts

Coding Interrupts in AVR C

Keep ISR short

Example Diagram (in-class):

Refer to RTOS notes, figures below note ** Keep ISRs Short that show effect of short vs long ISR on Task 1 and Task 2 timing

Use of volatile keyword for shared variable

Interaction of Interrupts with read-modify-write of variables shared with ISR

Consider the follow sequence:

code executionmemorymainmainISRISRccr16r16r0r0load c to r16100inc r16Interrupt Event+1=101load c to r0100addi r0,10+10=110store r0 to c110store r0 to c101

ISRs and multi-word code

Consider c = c + 1; as a 5 step process:

  1. Load low byte of c from memory to register
  2. Load high byte of c from memory to register
  3. perform increment
  4. Store low byte register to memory
  5. Store high byte register to memory

Consider the following sequence

code executionmemorymainmainISRISRccr17r17r16r16r1r1r0r0load low(c) to r160xFFload high(c) to r170x01add r16,1 (sets carry bit)+1=0x00addc r17,0+carry=0x02store r16 to high(c)low=0x00,c=0x0100Interrupt Eventload low(c) to r00x00load high(c) to r10x01c==0x1000response to equalitystore r17 to high(c)0x02

Atomic Operation for Resource Access

http://www.nongnu.org/avr-libc/user-manual/group__util__atomic.html#gaaaea265b31dabcfb3098bec7685c39e4 :

#include <inttypes.h> 
#include <avr/interrupt.h> 
#include <avr/io.h> 
#include <util/atomic.h> 
volatile uint16_t ctr; 
ISR(TIMER1_OVF_vect) { 
  ctr--; 
} 
 
... 
int 
main(void) { 
   ... 
   ctr = 0x200; 
   start_timer(); 
   sei(); 
   uint16_t ctr_copy; 
   do { 
      ATOMIC_BLOCK(ATOMIC_FORCEON)          
      { 
       ctr_copy = ctr; 
      } 
   } 
   while (ctr_copy != 0); 
   ... 
} 

Interrupt Enabling

Multiple Pending Interrupts in AVR (lower wins)

Interrupting ISRs

Interrupt Mask Registers

Clearing the Interrupt Flag (IRQ)

Interrupt Sequence (AVR)

Interrupt Response Time (AVR)

Questions for familiarizing yourself with a platform for ISR

What to look for when learning a new platform.

Slide Fixes:

2022-08: ## ISRs and multi-word code:  figure arrow note corrected :  hnote right of ISR: load ~~low~~ ++high++(c) to r1