L02 - AVR 8-bit Architecture

(Micro) processor, computer, controller

• CPU: is a unit that fetches and processes a set of general-purpose instructions.
• Microprocessor: is a CPU on a single chip. It may also have other units (e.g. caches, floating point processing arithmetic faster processing of instructions. (Intel 4004)
• Microcomputer: when a microprocessor + I/O + memory+ etc are put together to form a small computer for applications like data collection, or control application.
• Microcontroller (MCU): a microcomputer on a single chip. It brings together the microprocessor core and a rich collection of peripherals and I/O capability.

AVR Architecture

RISC Harvard Architecture

• RISC not CISC
• Harvard not Von Neumann
  • Separate Program and Data memory
  • On-chip flash memory-->program memory
    • execute in-place
  • On-chip data memory (RAM and EEPROM)
    
• 32 x 8 General purpose registers
• On-chip programmable timers
• Internal and external interrupt sources
• Programmable watchdog timer
• On-chip RC clock oscillator (more on clock later)
• Variety of I/O, Programmable I/O lines

General 8-Bit AVR Architecture Family

Many variants of the AVR 8-bit $\mu$C exist, differ in

• memory Size,

• I/Os,

• slightly in instruction set,

• power usage, voltage and clock

• Flash Program Memory stores the executed program on-chip
• Instruction Register holds the fetched instruction
• Control Lines are control signals that affect the operations being performed
• Instruction Decoder generates control signals for the other components
• Program Counter is a pointer into the instruction memory
• Data Bus 8-bit
• Status and Control registers reflect side-effects of operations (e.g. comparison) can affect operations (e.g. branch)
• 32x8 General Purpose Registers are 32 8-bit registers are weakly specialized
• Data SRAM
• EEPROM small amount of non-volatile memory (512 bytes on course's atmega169P)
• I/O Lines provide pathways to the external world
• Interrupt unit
• SPI Unit provides serial communication that can transfer data while processor performs other activity
• Watchdog Timer allow for automated system reset upon activity timeout
• Analog Comparator allows for basic analog input, analog signal monitoring, and analog event triggers
• I/O Modules might refer to other i/o capabilities such as other serial interfaces, lcd controllers

Pipeline

• AVR has a 2-stage pipeline (Fetch and Execute)

  • Decode happens in IF cycle

• Many instructions execute in a single clock cycle, and a few take 2 or more clock cycles.

  • Makes writing tight timing loops easy
  

  Time: Instruction	cycle 0	cycle 1	cycle 2	cycle 3	cycle 4
  Instruction 0	IF	EX
  Instruction 1		IF	EX
  Instruction 2			IF	EX
  Instruction 3				IF	EX
  Instruction 4					IF

Execution timing

• the single-cycle fetch execute and write-back is a defining aspect of the AVR

ATmega 169P

• ATmega169P is our case study for this course
• Full datasheet can be found at https://www.microchip.com/en-us/product/ATmega169P#document-table
• From megaAVR family: (VS tinyAVR, XMEGA, 32bit AVR)
• "P" in 169P means "Low Power"
• "16" in 169P refers to 16K program memory
• "9" is the design revision

ATmega169P Full Architecture

Source: AVR Data sheet

Program Memory Map

• The ATmega169P contains 16 Kbytes Flash memory for program storage.

• All AVR instructions are 16 or 32 bits wide, Therefore the Flash is organized as 8K × 16.

• 8K = 2^13 --> 13 bits are required for addressing the program memory

• Program Counter (PC) = 13 bits

Data Memory Map (DMP)

• Entire Data Memory Space shown here can be accessed as memory

  • register and I/O register related instructions is faster on the real registers.

• General Purpose Registers:

  • 32 General Registers labeled R0...R31
  • Altogether called the Register File
    • Most can be generally use in instructions: e.g. ADD R2, R3

• Make sure to look at Section 30. Register Summary" of Data sheet for complete details

Special Function Registers (SFRs)

• SFRs include:
  • I/O Registers
  • Timers
  • Stack Pointers
  • Program Counter
• Some SFRs are not writeable by instructions
• I/O Registers
• Can be accessed using LDs and STs
• Some are bit accessible using SBI and CBI

I/O Registers

• All I/O locations may be accessed by memory instructions LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space.
• 64 I/O Registers
  • Different Memory address than I/O address (e.g. I/O Register zero(0x0) is data memory address (0x20) )
  • 0x00 (0x20)-- 0x1F(0x3F) are bit- accessible using "SBI" and "CBI" instructions.
  • 0x00(0x20)-0x3F(0x5F) can be accessed using "IN" and "OUT" instructions.
  • When addressing I/O Registers as data space using LD and ST instructions, Data memory address must be used (e.g. 0x20 instead of 0x0 )
• 160 Extended I/O Registers
  • 0x60 - 0xFF in SRAM
  • Only ST/STS/STD and LD/LDS/LDD instructions can be used.

SRAM Access Time

(Overview, will review instructs in detail later)

• 2 cycles
• Address pointers (Registers X, Y, Z) are used for addressing
• At first cycle, register file is accessed. At the end of the first cycle, the ALU performs address calculation.
• At second cycle, calculated address is used to access the SRAM location (to read or write)

EEPROM Space

• 100,000 write/erase cycles

• Read operation halts the CPU for four clock cycles. (after 4 cycles next instruction is executed)

• Write operation halts the CPU for two clock cycles.

• Can be accessed through EEPROM register manipulations (I/O registers)

  1. EEPROM Address Register (0x41) & (0x42)

  2. EEPROM Data Register (0x40)

  3. EEPROM Control Register (0x3F)

• (EEPROM Details will be covered later)