Lecture 06 – More AVR Assembly

Ryan Robucci

Lecture 06 – More AVR Assembly

Needs Update

I have discovered that some of the links are dead, maybe even dangerous. As a precaution I have omitted some references. I will update this document soon.
Some of the code is for an older gcc assembler, but the concepts remain. I will update as appropriate if we stay with the new toolchain.

Assembler

This semester we are using an assembler which follows a syntax based on the GNU assembler

Manual:

https://sourceware.org/binutils/docs/
- MultiPage: https://sourceware.org/binutils/docs/as/index.html
- Single Page: https://sourceware.org/binutils/docs/as.html
- PDF: https://sourceware.org/binutils/docs/as.pdf
  AVR-Specific Documentation
https://sourceware.org/binutils/docs-2.21/as/AVR_002dDependent.html#AVR_002dDependent

Information about the GNU Assembler

https://en.wikipedia.org/wiki/GNU_Assembler

GNU AS is not AVR ASM

You would more commonly find avr-assembler code

Device-Specific Header/Include File

To support assembly and C code, each microcontroller will be have an accompanying include file providing items like the following which define the register-level API

register and memory addresses defined with values
named bit positions and field masks, offsets, and lengths
memory ranges, like start-of-RAM
memeory address for memory-mapped peripherals
special constants like control commands, and named values for control bits
"m169Pdef.inc" includes register and bit definitions for the ATmega169P

Excerpt:

following has been modified to conform to GNU AS syntax, since m169Pdef.inc is provided for avrasm

;* When including this file in the assembly program file, all I/O register  
;* names and I/O register bit names appearing in the data book can be used. 
;* In addition, the six registers forming the three data pointers X, Y and  
;* Z have been assigned names XL - ZH. Highest RAM address for Internal  
;* SRAM is also defined 
;*  
;* The Register names are represented by their hexadecimal address. 
;*  
;* The Register Bit names are represented by their bit number (0-7).

...

.equ DDRB , 0x04 
.equ PINB , 0x03 
.equ PORTA , 0x02 
.equ DDRA , 0x01

...

.equ PORTB1, 1 ; Port B Data Register bit 1 
.equ PB1 , 1 ; For compatibility

allows for

in    r16,PORTB             ;read PORTB latch 
sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 
out   PORTB,r16             ;output to PORTB

sbr and ori are synonyms

.equ TIFR0 , 0x15

; TIFR0 - Timer/Counter0 Interrupt Flag register 
.equ TOV0 , 0 ; Timer/Counter0 Overflow Flag 
.equ OCF0A , 1 ; Timer/Counter0 Output Compare Flag 0

allows for

in    r16,TIFR0              ;read the Timer Interrupt Flag Register 
sbrc  r16,TOV0               ;test the overflow flag (use bit#) 
rjmp  TOV0_is_set            ;jump if set 
 ...                         ;otherwise do something else

.equ SRAM_START , 0x0100 
.equ SRAM_SIZE , 1024 
.equ RAMEND , 0x04ff

allows for

LDI R0, HIGH(RAMEND) ; upper byte 
OUT SPH,R0           ;  
LDI R0, LOW(RAMEND)  ; lower byte 
OUT SPL,R0

m169pdef.inc listing

(avrasm syntax)

m169pdef.inc listing, click to expand

;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 

;***** Created: 2011-02-09 12:03 ******* Source: ATmega169P.xml ********** 

;************************************************************************* 

;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y 

;*  

;* Number            : AVR000 

;* File Name         : "m169Pdef.inc" 

;* Title             : Register/Bit Definitions for the ATmega169P 

;* Date              : 2011-02-09 

;* Version           : 2.35 

;* Support E-mail    : avr@atmel.com 

;* Target MCU        : ATmega169P 

;*  

;* DESCRIPTION 

;* When including this file in the assembly program file, all I/O register  

;* names and I/O register bit names appearing in the data book can be used. 

;* In addition, the six registers forming the three data pointers X, Y and  

;* Z have been assigned names XL - ZH. Highest RAM address for Internal  

;* SRAM is also defined  

;*  

;* The Register names are represented by their hexadecimal address. 

;*  

;* The Register Bit names are represented by their bit number (0-7). 

;*  

;* Please observe the difference in using the bit names with instructions 

;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 

;* (skip if bit in register set/cleared). The following example illustrates 

;* this: 

;*  

;* in    r16,PORTB             ;read PORTB latch 

;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 

;* out   PORTB,r16             ;output to PORTB 

;*  

;* in    r16,TIFR              ;read the Timer Interrupt Flag Register 

;* sbrc  r16,TOV0              ;test the overflow flag (use bit#) 

;* rjmp  TOV0_is_set           ;jump if set 

;* ...                         ;otherwise do something else 

;************************************************************************* 

 

#ifndef _M169PDEF_INC_ 

#define _M169PDEF_INC_ 

 

 

#pragma partinc 0 

 

; ***** SPECIFY DEVICE *************************************************** 

.device ATmega169P 

#pragma AVRPART ADMIN PART_NAME ATmega169P 

.equ SIGNATURE_000 = 0x1e 

.equ SIGNATURE_001 = 0x94 

.equ SIGNATURE_002 = 0x05 

 

#pragma AVRPART CORE CORE_VERSION V2E 

 

 

; ***** I/O REGISTER DEFINITIONS ***************************************** 

; NOTE: 

; Definitions marked "MEMORY MAPPED"are extended I/O ports 

  embed_svg: false
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@import "../custom/lecture.less"

<!-- xslide -->

; and cannot be used with IN/OUT instructions 

.equ LCDDR18 = 0xfe ; MEMORY MAPPED 

.equ LCDDR17 = 0xfd ; MEMORY MAPPED 

.equ LCDDR16 = 0xfc ; MEMORY MAPPED 

.equ LCDDR15 = 0xfb ; MEMORY MAPPED 

.equ LCDDR13 = 0xf9 ; MEMORY MAPPED 

.equ LCDDR12 = 0xf8 ; MEMORY MAPPED 

.equ LCDDR11 = 0xf7 ; MEMORY MAPPED 

.equ LCDDR10 = 0xf6 ; MEMORY MAPPED 

.equ LCDDR8 = 0xf4 ; MEMORY MAPPED 

.equ LCDDR7 = 0xf3 ; MEMORY MAPPED 

.equ LCDDR6 = 0xf2 ; MEMORY MAPPED 

.equ LCDDR5 = 0xf1 ; MEMORY MAPPED 

.equ LCDDR3 = 0xef ; MEMORY MAPPED 

.equ LCDDR2 = 0xee ; MEMORY MAPPED 

.equ LCDDR1 = 0xed ; MEMORY MAPPED 

.equ LCDDR0 = 0xec ; MEMORY MAPPED 

.equ LCDCCR = 0xe7 ; MEMORY MAPPED 

.equ LCDFRR = 0xe6 ; MEMORY MAPPED 

.equ LCDCRB = 0xe5 ; MEMORY MAPPED 

.equ LCDCRA = 0xe4 ; MEMORY MAPPED 

.equ UDR0 = 0xc6 ; MEMORY MAPPED 

.equ UBRR0L = 0xc4 ; MEMORY MAPPED 

.equ UBRR0H = 0xc5 ; MEMORY MAPPED 

.equ UCSR0C = 0xc2 ; MEMORY MAPPED 

.equ UCSR0B = 0xc1 ; MEMORY MAPPED 

.equ UCSR0A = 0xc0 ; MEMORY MAPPED 

.equ USIDR = 0xba ; MEMORY MAPPED 

.equ USISR = 0xb9 ; MEMORY MAPPED 

.equ USICR = 0xb8 ; MEMORY MAPPED 

.equ ASSR = 0xb6 ; MEMORY MAPPED 

.equ OCR2A = 0xb3 ; MEMORY MAPPED 

.equ TCNT2 = 0xb2 ; MEMORY MAPPED 

.equ TCCR2B = 0xb1 ; MEMORY MAPPED 

.equ TCCR2A = 0xb0 ; MEMORY MAPPED 

.equ OCR1BL = 0x8a ; MEMORY MAPPED 

.equ OCR1BH = 0x8b ; MEMORY MAPPED 

.equ OCR1AL = 0x88 ; MEMORY MAPPED 

.equ OCR1AH = 0x89 ; MEMORY MAPPED 

.equ ICR1L = 0x86 ; MEMORY MAPPED 

.equ ICR1H = 0x87 ; MEMORY MAPPED 

.equ TCNT1L = 0x84 ; MEMORY MAPPED 

.equ TCNT1H = 0x85 ; MEMORY MAPPED 

.equ TCCR1C = 0x82 ; MEMORY MAPPED 

.equ TCCR1B = 0x81 ; MEMORY MAPPED 

.equ TCCR1A = 0x80 ; MEMORY MAPPED 

.equ DIDR1 = 0x7f ; MEMORY MAPPED 

.equ DIDR0 = 0x7e ; MEMORY MAPPED 

.equ ADMUX = 0x7c ; MEMORY MAPPED 

.equ ADCSRB = 0x7b ; MEMORY MAPPED 

.equ ADCSRA = 0x7a ; MEMORY MAPPED 

.equ ADCH = 0x79 ; MEMORY MAPPED 

.equ ADCL = 0x78 ; MEMORY MAPPED 

.equ TIMSK2 = 0x70 ; MEMORY MAPPED 

.equ TIMSK1 = 0x6f ; MEMORY MAPPED 

.equ TIMSK0 = 0x6e ; MEMORY MAPPED 

.equ PCMSK0 = 0x6b ; MEMORY MAPPED 

.equ PCMSK1 = 0x6c ; MEMORY MAPPED 

.equ EICRA = 0x69 ; MEMORY MAPPED 

.equ OSCCAL = 0x66 ; MEMORY MAPPED 

.equ PRR = 0x64 ; MEMORY MAPPED 

.equ CLKPR = 0x61 ; MEMORY MAPPED 

.equ WDTCR = 0x60 ; MEMORY MAPPED 

.equ SREG = 0x3f 

.equ SPL = 0x3d 

.equ SPH = 0x3e 

.equ SPMCSR = 0x37 

.equ MCUCR = 0x35 

.equ MCUSR = 0x34 

.equ SMCR = 0x33 

.equ OCDR = 0x31 

.equ ACSR = 0x30 

.equ SPDR = 0x2e 

.equ SPSR = 0x2d 

.equ SPCR = 0x2c 

.equ GPIOR2 = 0x2b 

.equ GPIOR1 = 0x2a 

.equ OCR0A = 0x27 

.equ TCNT0 = 0x26 

.equ TCCR0A = 0x24 

.equ GTCCR = 0x23 

.equ EEARL = 0x21 

.equ EEARH = 0x22 

.equ EEDR = 0x20 

.equ EECR = 0x1f 

.equ GPIOR0 = 0x1e 

.equ EIMSK = 0x1d 

.equ EIFR = 0x1c 

.equ TIFR2 = 0x17 

.equ TIFR1 = 0x16 

.equ TIFR0 = 0x15 

.equ PORTG = 0x14 

.equ DDRG = 0x13 

.equ PING = 0x12 

.equ PORTF = 0x11 

.equ DDRF = 0x10 

.equ PINF = 0x0f 

.equ PORTE = 0x0e 

.equ DDRE = 0x0d 

.equ PINE = 0x0c 

.equ PORTD = 0x0b 

.equ DDRD = 0x0a 

.equ PIND = 0x09 

.equ PORTC = 0x08 

.equ DDRC = 0x07 

.equ PINC = 0x06 

.equ PORTB = 0x05 

.equ DDRB = 0x04 

.equ PINB = 0x03 

.equ PORTA = 0x02 

.equ DDRA = 0x01 

.equ PINA = 0x00 

 

 

; ***** BIT DEFINITIONS ************************************************** 

 

; ***** TIMER_COUNTER_0 ************** 

; TCCR0A - Timer/Counter0 Control Register 

.equ CS00 = 0 ; Clock Select 0 

.equ CS01 = 1 ; Clock Select 1 

.equ CS02 = 2 ; Clock Select 2 

.equ WGM01 = 3 ; Waveform Generation Mode 1 

.equ COM0A0 = 4 ; Compare match Output Mode 0 

.equ COM0A1 = 5 ; Compare Match Output Mode 1 

.equ WGM00 = 6 ; Waveform Generation Mode 0 

.equ FOC0A = 7 ; Force Output Compare 

 

; TCNT0 - Timer/Counter0 

.equ TCNT0_0 = 0 ;  

.equ TCNT0_1 = 1 ;  

.equ TCNT0_2 = 2 ;  

.equ TCNT0_3 = 3 ;  

.equ TCNT0_4 = 4 ;  

.equ TCNT0_5 = 5 ;  

.equ TCNT0_6 = 6 ;  

.equ TCNT0_7 = 7 ;  

 

; OCR0A - Timer/Counter0 Output Compare Register 

.equ OCR0A0 = 0 ;  

.equ OCR0A1 = 1 ;  

.equ OCR0A2 = 2 ;  

.equ OCR0A3 = 3 ;  

.equ OCR0A4 = 4 ;  

.equ OCR0A5 = 5 ;  

.equ OCR0A6 = 6 ;  

.equ OCR0A7 = 7 ;  

 

; TIMSK0 - Timer/Counter0 Interrupt Mask Register 

.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable 

.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable 

 

; TIFR0 - Timer/Counter0 Interrupt Flag register 

.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag 

.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0 

 

; GTCCR - General Timer/Control Register 

.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 

.equ PSR10 = PSR310 ; For compatibility 

.equ PSR0 = PSR310 ; For compatibility 

.equ PSR1 = PSR310 ; For compatibility 

.equ PSR3 = PSR310 ; For compatibility 

.equ TSM = 7 ; Timer/Counter Synchronization Mode 

 

 

; ***** TIMER_COUNTER_1 ************** 

; TIMSK1 - Timer/Counter1 Interrupt Mask Register 

.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable 

.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable 

.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable 

.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable 

 

; TIFR1 - Timer/Counter1 Interrupt Flag register 

.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag 

.equ OCF1A = 1 ; Output Compare Flag 1A 

.equ OCF1B = 2 ; Output Compare Flag 1B 

.equ ICF1 = 5 ; Input Capture Flag 1 

 

; TCCR1A - Timer/Counter1 Control Register A 

.equ WGM10 = 0 ; Waveform Generation Mode 

.equ WGM11 = 1 ; Waveform Generation Mode 

.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 

.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 

.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 

.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 

 

; TCCR1B - Timer/Counter1 Control Register B 

.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 

.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 

.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 

.equ WGM12 = 3 ; Waveform Generation Mode 

.equ WGM13 = 4 ; Waveform Generation Mode 

.equ ICES1 = 6 ; Input Capture 1 Edge Select 

.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler 

 

; TCCR1C - Timer/Counter 1 Control Register C 

.equ FOC1B = 6 ; Force Output Compare 1B 

.equ FOC1A = 7 ; Force Output Compare 1A 

 

 

; ***** TIMER_COUNTER_2 ************** 

; TIMSK2 - Timer/Counter2 Interrupt Mask register 

.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable 

.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable 

 

; TIFR2 - Timer/Counter2 Interrupt Flag Register 

.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag 

.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2 

 

; TCCR2A - Timer/Counter2 Control Register 

.equ CS20 = 0 ; Clock Select bit 0 

.equ CS21 = 1 ; Clock Select bit 1 

.equ CS22 = 2 ; Clock Select bit 2 

.equ WGM21 = 3 ; Waveform Generation Mode 

.equ COM2A0 = 4 ; Compare Output Mode bit 0 

.equ COM2A1 = 5 ; Compare Output Mode bit 1 

.equ WGM20 = 6 ; Waveform Generation Mode 

.equ FOC2A = 7 ; Force Output Compare A 

 

; TCNT2 - Timer/Counter2 

.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 

.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 

.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 

.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 

.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 

.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 

.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 

.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 

 

; OCR2A - Timer/Counter2 Output Compare Register 

.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 

.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 

.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 

.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 

.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 

.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 

.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 

.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 

 

; GTCCR - General Timer/Counter Control Register 

.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 

 

; ASSR - Asynchronous Status Register 

.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy 

.equ OCR2UB = 1 ; Output Compare Register2 Update Busy 

.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy 

.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2 

.equ EXCLK = 4 ; Enable External Clock Interrupt 

 

 

; ***** WATCHDOG ********************* 

; WDTCR - Watchdog Timer Control Register 

.equ WDTCSR = WDTCR ; For compatibility 

.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 

.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 

.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 

.equ WDE = 3 ; Watch Dog Enable 

.equ WDCE = 4 ; Watchdog Change Enable 

.equ WDTOE = WDCE ; For compatibility 

 

 

; ***** EEPROM *********************** 

; EEDR - EEPROM Data Register 

.equ EEDR0 = 0 ; EEPROM Data Register bit 0 

.equ EEDR1 = 1 ; EEPROM Data Register bit 1 

.equ EEDR2 = 2 ; EEPROM Data Register bit 2 

.equ EEDR3 = 3 ; EEPROM Data Register bit 3 

.equ EEDR4 = 4 ; EEPROM Data Register bit 4 

.equ EEDR5 = 5 ; EEPROM Data Register bit 5 

.equ EEDR6 = 6 ; EEPROM Data Register bit 6 

.equ EEDR7 = 7 ; EEPROM Data Register bit 7 

 

; EECR - EEPROM Control Register 

.equ EERE = 0 ; EEPROM Read Enable 

.equ EEWE = 1 ; EEPROM Write Enable 

.equ EEMWE = 2 ; EEPROM Master Write Enable 

.equ EEWEE = EEMWE ; For compatibility 

.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 

 

 

; ***** SPI ************************** 

; SPDR - SPI Data Register 

.equ SPDR0 = 0 ; SPI Data Register bit 0 

.equ SPDR1 = 1 ; SPI Data Register bit 1 

.equ SPDR2 = 2 ; SPI Data Register bit 2 

.equ SPDR3 = 3 ; SPI Data Register bit 3 

.equ SPDR4 = 4 ; SPI Data Register bit 4 

.equ SPDR5 = 5 ; SPI Data Register bit 5 

.equ SPDR6 = 6 ; SPI Data Register bit 6 

.equ SPDR7 = 7 ; SPI Data Register bit 7 

 

; SPSR - SPI Status Register 

.equ SPI2X = 0 ; Double SPI Speed Bit 

.equ WCOL = 6 ; Write Collision Flag 

.equ SPIF = 7 ; SPI Interrupt Flag 

 

; SPCR - SPI Control Register 

.equ SPR0 = 0 ; SPI Clock Rate Select 0 

.equ SPR1 = 1 ; SPI Clock Rate Select 1 

.equ CPHA = 2 ; Clock Phase 

.equ CPOL = 3 ; Clock polarity 

.equ MSTR = 4 ; Master/Slave Select 

.equ DORD = 5 ; Data Order 

.equ SPE = 6 ; SPI Enable 

.equ SPIE = 7 ; SPI Interrupt Enable 

 

 

; ***** PORTA ************************ 

; PORTA - Port A Data Register 

.equ PORTA0 = 0 ; Port A Data Register bit 0 

.equ PA0 = 0 ; For compatibility 

.equ PORTA1 = 1 ; Port A Data Register bit 1 

.equ PA1 = 1 ; For compatibility 

.equ PORTA2 = 2 ; Port A Data Register bit 2 

.equ PA2 = 2 ; For compatibility 

.equ PORTA3 = 3 ; Port A Data Register bit 3 

.equ PA3 = 3 ; For compatibility 

.equ PORTA4 = 4 ; Port A Data Register bit 4 

.equ PA4 = 4 ; For compatibility 

.equ PORTA5 = 5 ; Port A Data Register bit 5 

.equ PA5 = 5 ; For compatibility 

.equ PORTA6 = 6 ; Port A Data Register bit 6 

.equ PA6 = 6 ; For compatibility 

.equ PORTA7 = 7 ; Port A Data Register bit 7 

.equ PA7 = 7 ; For compatibility 

 

; DDRA - Port A Data Direction Register 

.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 

.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 

.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 

.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 

.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 

.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 

.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 

.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 

 

; PINA - Port A Input Pins 

.equ PINA0 = 0 ; Input Pins, Port A bit 0 

.equ PINA1 = 1 ; Input Pins, Port A bit 1 

.equ PINA2 = 2 ; Input Pins, Port A bit 2 

.equ PINA3 = 3 ; Input Pins, Port A bit 3 

.equ PINA4 = 4 ; Input Pins, Port A bit 4 

.equ PINA5 = 5 ; Input Pins, Port A bit 5 

.equ PINA6 = 6 ; Input Pins, Port A bit 6 

.equ PINA7 = 7 ; Input Pins, Port A bit 7 

 

 

; ***** PORTB ************************ 

; PORTB - Port B Data Register 

.equ PORTB0 = 0 ; Port B Data Register bit 0 

.equ PB0 = 0 ; For compatibility 

.equ PORTB1 = 1 ; Port B Data Register bit 1 

.equ PB1 = 1 ; For compatibility 

.equ PORTB2 = 2 ; Port B Data Register bit 2 

.equ PB2 = 2 ; For compatibility 

.equ PORTB3 = 3 ; Port B Data Register bit 3 

.equ PB3 = 3 ; For compatibility 

.equ PORTB4 = 4 ; Port B Data Register bit 4 

.equ PB4 = 4 ; For compatibility 

.equ PORTB5 = 5 ; Port B Data Register bit 5 

.equ PB5 = 5 ; For compatibility 

.equ PORTB6 = 6 ; Port B Data Register bit 6 

.equ PB6 = 6 ; For compatibility 

.equ PORTB7 = 7 ; Port B Data Register bit 7 

.equ PB7 = 7 ; For compatibility 

 

; DDRB - Port B Data Direction Register 

.equ DDB0 = 0 ; Port B Data Direction Register bit 0 

.equ DDB1 = 1 ; Port B Data Direction Register bit 1 

.equ DDB2 = 2 ; Port B Data Direction Register bit 2 

.equ DDB3 = 3 ; Port B Data Direction Register bit 3 

.equ DDB4 = 4 ; Port B Data Direction Register bit 4 

.equ DDB5 = 5 ; Port B Data Direction Register bit 5 

.equ DDB6 = 6 ; Port B Data Direction Register bit 6 

.equ DDB7 = 7 ; Port B Data Direction Register bit 7 

 

; PINB - Port B Input Pins 

.equ PINB0 = 0 ; Port B Input Pins bit 0 

.equ PINB1 = 1 ; Port B Input Pins bit 1 

.equ PINB2 = 2 ; Port B Input Pins bit 2 

.equ PINB3 = 3 ; Port B Input Pins bit 3 

.equ PINB4 = 4 ; Port B Input Pins bit 4 

.equ PINB5 = 5 ; Port B Input Pins bit 5 

.equ PINB6 = 6 ; Port B Input Pins bit 6 

.equ PINB7 = 7 ; Port B Input Pins bit 7 

 

 

; ***** PORTC ************************ 

; PORTC - Port C Data Register 

.equ PORTC0 = 0 ; Port C Data Register bit 0 

.equ PC0 = 0 ; For compatibility 

.equ PORTC1 = 1 ; Port C Data Register bit 1 

.equ PC1 = 1 ; For compatibility 

.equ PORTC2 = 2 ; Port C Data Register bit 2 

.equ PC2 = 2 ; For compatibility 

.equ PORTC3 = 3 ; Port C Data Register bit 3 

.equ PC3 = 3 ; For compatibility 

.equ PORTC4 = 4 ; Port C Data Register bit 4 

.equ PC4 = 4 ; For compatibility 

.equ PORTC5 = 5 ; Port C Data Register bit 5 

.equ PC5 = 5 ; For compatibility 

.equ PORTC6 = 6 ; Port C Data Register bit 6 

.equ PC6 = 6 ; For compatibility 

.equ PORTC7 = 7 ; Port C Data Register bit 7 

.equ PC7 = 7 ; For compatibility 

 

; DDRC - Port C Data Direction Register 

.equ DDC0 = 0 ; Port C Data Direction Register bit 0 

.equ DDC1 = 1 ; Port C Data Direction Register bit 1 

.equ DDC2 = 2 ; Port C Data Direction Register bit 2 

.equ DDC3 = 3 ; Port C Data Direction Register bit 3 

.equ DDC4 = 4 ; Port C Data Direction Register bit 4 

.equ DDC5 = 5 ; Port C Data Direction Register bit 5 

.equ DDC6 = 6 ; Port C Data Direction Register bit 6 

.equ DDC7 = 7 ; Port C Data Direction Register bit 7 

 

; PINC - Port C Input Pins 

.equ PINC0 = 0 ; Port C Input Pins bit 0 

.equ PINC1 = 1 ; Port C Input Pins bit 1 

.equ PINC2 = 2 ; Port C Input Pins bit 2 

.equ PINC3 = 3 ; Port C Input Pins bit 3 

.equ PINC4 = 4 ; Port C Input Pins bit 4 

.equ PINC5 = 5 ; Port C Input Pins bit 5 

.equ PINC6 = 6 ; Port C Input Pins bit 6 

.equ PINC7 = 7 ; Port C Input Pins bit 7 

 

 

; ***** PORTD ************************ 

; PORTD - Port D Data Register 

.equ PORTD0 = 0 ; Port D Data Register bit 0 

.equ PD0 = 0 ; For compatibility 

.equ PORTD1 = 1 ; Port D Data Register bit 1 

.equ PD1 = 1 ; For compatibility 

.equ PORTD2 = 2 ; Port D Data Register bit 2 

.equ PD2 = 2 ; For compatibility 

.equ PORTD3 = 3 ; Port D Data Register bit 3 

.equ PD3 = 3 ; For compatibility 

.equ PORTD4 = 4 ; Port D Data Register bit 4 

.equ PD4 = 4 ; For compatibility 

.equ PORTD5 = 5 ; Port D Data Register bit 5 

.equ PD5 = 5 ; For compatibility 

.equ PORTD6 = 6 ; Port D Data Register bit 6 

.equ PD6 = 6 ; For compatibility 

.equ PORTD7 = 7 ; Port D Data Register bit 7 

.equ PD7 = 7 ; For compatibility 

 

; DDRD - Port D Data Direction Register 

.equ DDD0 = 0 ; Port D Data Direction Register bit 0 

.equ DDD1 = 1 ; Port D Data Direction Register bit 1 

.equ DDD2 = 2 ; Port D Data Direction Register bit 2 

.equ DDD3 = 3 ; Port D Data Direction Register bit 3 

.equ DDD4 = 4 ; Port D Data Direction Register bit 4 

.equ DDD5 = 5 ; Port D Data Direction Register bit 5 

.equ DDD6 = 6 ; Port D Data Direction Register bit 6 

.equ DDD7 = 7 ; Port D Data Direction Register bit 7 

 

; PIND - Port D Input Pins 

.equ PIND0 = 0 ; Port D Input Pins bit 0 

.equ PIND1 = 1 ; Port D Input Pins bit 1 

.equ PIND2 = 2 ; Port D Input Pins bit 2 

.equ PIND3 = 3 ; Port D Input Pins bit 3 

.equ PIND4 = 4 ; Port D Input Pins bit 4 

.equ PIND5 = 5 ; Port D Input Pins bit 5 

.equ PIND6 = 6 ; Port D Input Pins bit 6 

.equ PIND7 = 7 ; Port D Input Pins bit 7 

 

 

; ***** ANALOG_COMPARATOR ************ 

; ADCSRB - ADC Control and Status Register B 

.equ ACME = 6 ; Analog Comparator Multiplexer Enable 

 

; ACSR - Analog Comparator Control And Status Register 

.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 

.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 

.equ ACIC = 2 ; Analog Comparator Input Capture Enable 

.equ ACIE = 3 ; Analog Comparator Interrupt Enable 

.equ ACI = 4 ; Analog Comparator Interrupt Flag 

.equ ACO = 5 ; Analog Compare Output 

.equ ACBG = 6 ; Analog Comparator Bandgap Select 

.equ ACD = 7 ; Analog Comparator Disable 

 

; DIDR1 - Digital Input Disable Register 1 

.equ AIN0D = 0 ; AIN0 Digital Input Disable 

.equ AIN1D = 1 ; AIN1 Digital Input Disable 

 

 

; ***** PORTE ************************ 

; PORTE - Data Register, Port E 

.equ PORTE0 = 0 ;  

.equ PE0 = 0 ; For compatibility 

.equ PORTE1 = 1 ;  

.equ PE1 = 1 ; For compatibility 

.equ PORTE2 = 2 ;  

.equ PE2 = 2 ; For compatibility 

.equ PORTE3 = 3 ;  

.equ PE3 = 3 ; For compatibility 

.equ PORTE4 = 4 ;  

.equ PE4 = 4 ; For compatibility 

.equ PORTE5 = 5 ;  

.equ PE5 = 5 ; For compatibility 

.equ PORTE6 = 6 ;  

.equ PE6 = 6 ; For compatibility 

.equ PORTE7 = 7 ;  

.equ PE7 = 7 ; For compatibility 

 

; DDRE - Data Direction Register, Port E 

.equ DDE0 = 0 ;  

.equ DDE1 = 1 ;  

.equ DDE2 = 2 ;  

.equ DDE3 = 3 ;  

.equ DDE4 = 4 ;  

.equ DDE5 = 5 ;  

.equ DDE6 = 6 ;  

.equ DDE7 = 7 ;  

 

; PINE - Input Pins, Port E 

.equ PINE0 = 0 ;  

.equ PINE1 = 1 ;  

.equ PINE2 = 2 ;  

.equ PINE3 = 3 ;  

.equ PINE4 = 4 ;  

.equ PINE5 = 5 ;  

.equ PINE6 = 6 ;  

.equ PINE7 = 7 ;  

 

 

; ***** PORTF ************************ 

; PORTF - Data Register, Port F 

.equ PORTF0 = 0 ;  

.equ PF0 = 0 ; For compatibility 

.equ PORTF1 = 1 ;  

.equ PF1 = 1 ; For compatibility 

.equ PORTF2 = 2 ;  

.equ PF2 = 2 ; For compatibility 

.equ PORTF3 = 3 ;  

.equ PF3 = 3 ; For compatibility 

.equ PORTF4 = 4 ;  

.equ PF4 = 4 ; For compatibility 

.equ PORTF5 = 5 ;  

.equ PF5 = 5 ; For compatibility 

.equ PORTF6 = 6 ;  

.equ PF6 = 6 ; For compatibility 

.equ PORTF7 = 7 ;  

.equ PF7 = 7 ; For compatibility 

 

; DDRF - Data Direction Register, Port F 

.equ DDF0 = 0 ;  

.equ DDF1 = 1 ;  

.equ DDF2 = 2 ;  

.equ DDF3 = 3 ;  

.equ DDF4 = 4 ;  

.equ DDF5 = 5 ;  

.equ DDF6 = 6 ;  

.equ DDF7 = 7 ;  

 

; PINF - Input Pins, Port F 

.equ PINF0 = 0 ;  

.equ PINF1 = 1 ;  

.equ PINF2 = 2 ;  

.equ PINF3 = 3 ;  

.equ PINF4 = 4 ;  

.equ PINF5 = 5 ;  

.equ PINF6 = 6 ;  

.equ PINF7 = 7 ;  

 

 

; ***** JTAG ************************* 

; OCDR - On-Chip Debug Related Register in I/O Memory 

.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 

.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 

.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 

.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 

.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 

.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 

.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 

.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 

.equ IDRD = OCDR7 ; For compatibility 

 

; MCUCR - MCU Control Register 

.equ JTD = 7 ; JTAG Interface Disable 

 

; MCUSR - MCU Status Register 

.equ JTRF = 4 ; JTAG Reset Flag 

 

 

; ***** LCD ************************** 

; LCDCRA - LCD Control Register A 

.equ LCDBL = 0 ; LCD Blanking 

.equ LCDCCD = 1 ; LCD Contrast Control Disable 

.equ LCDBD = 2 ; LCD Buffer Disable 

.equ LCDIE = 3 ; LCD Interrupt Enable 

.equ LCDIF = 4 ; LCD Interrupt Flag 

.equ LCDAB = 6 ; LCD A or B waveform 

.equ LCDEN = 7 ; LCD Enable 

 

; LCDCRB - LCD Control and Status Register B 

.equ LCDPM0 = 0 ; LCD Port Mask 0 

.equ LCDPM1 = 1 ; LCD Port Mask 1 

.equ LCDPM2 = 2 ; LCD Port Mask 2 

.equ LCDMUX0 = 4 ; LCD Mux Select 0 

.equ LCDMUX1 = 5 ; LCD Mux Select 1 

.equ LCD2B = 6 ; LCD 1/2 Bias Select 

.equ LCDCS = 7 ; LCD CLock Select 

 

; LCDFRR - LCD Frame Rate Register 

.equ LCDCD0 = 0 ; LCD Clock Divider 0 

.equ LCDCD1 = 1 ; LCD Clock Divider 1 

.equ LCDCD2 = 2 ; LCD Clock Divider 2 

.equ LCDPS0 = 4 ; LCD Prescaler Select 0 

.equ LCDPS1 = 5 ; LCD Prescaler Select 1 

.equ LCDPS2 = 6 ; LCD Prescaler Select 2 

 

; LCDCCR - LCD Contrast Control Register 

.equ LCDCC0 = 0 ; LCD Contrast Control 0 

.equ LCDCC1 = 1 ; LCD Contrast Control 1 

.equ LCDCC2 = 2 ; LCD Contrast Control 2 

.equ LCDCC3 = 3 ; LCD Contrast Control 3 

.equ LCDMDT = 4 ; LCD Maximum Drive Time 

.equ LCDDC0 = 5 ; LCD Display Configuration Bit 0 

.equ LCDDC1 = 6 ; LCD Display Configuration Bit 1 

.equ LCDDC2 = 7 ; LCD Display Configuration Bit 2 

 

; LCDDR18 - LCD Data Register 18 

.equ SEG324 = 0 ;  

 

; LCDDR17 - LCD Data Register 17 

.equ SEG316 = 0 ;  

.equ SEG317 = 1 ;  

.equ SEG318 = 2 ;  

.equ SEG319 = 3 ;  

.equ SEG320 = 4 ;  

.equ SEG321 = 5 ;  

.equ SEG322 = 6 ;  

.equ SEG323 = 7 ;  

 

; LCDDR16 - LCD Data Register 16 

.equ SEG308 = 0 ;  

.equ SEG309 = 1 ;  

.equ SEG310 = 2 ;  

.equ SEG311 = 3 ;  

.equ SEG312 = 4 ;  

.equ SEG313 = 5 ;  

.equ SEG314 = 6 ;  

.equ SEG315 = 7 ;  

 

; LCDDR15 - LCD Data Register 15 

.equ SEG300 = 0 ;  

.equ SEG301 = 1 ;  

.equ SEG302 = 2 ;  

.equ SEG303 = 3 ;  

.equ SEG304 = 4 ;  

.equ SEG305 = 5 ;  

.equ SEG306 = 6 ;  

.equ SEG307 = 7 ;  

 

; LCDDR13 - LCD Data Register 13 

.equ SEG224 = 0 ;  

 

; LCDDR12 - LCD Data Register 12 

.equ SEG216 = 0 ;  

.equ SEG217 = 1 ;  

.equ SEG218 = 2 ;  

.equ SEG219 = 3 ;  

.equ SEG220 = 4 ;  

.equ SEG221 = 5 ;  

.equ SEG222 = 6 ;  

.equ SEG223 = 7 ;  

 

; LCDDR11 - LCD Data Register 11 

.equ SEG208 = 0 ;  

.equ SEG209 = 1 ;  

.equ SEG210 = 2 ;  

.equ SEG211 = 3 ;  

.equ SEG212 = 4 ;  

.equ SEG213 = 5 ;  

.equ SEG214 = 6 ;  

.equ SEG215 = 7 ;  

 

; LCDDR10 - LCD Data Register 10 

.equ SEG200 = 0 ;  

.equ SEG201 = 1 ;  

.equ SEG202 = 2 ;  

.equ SEG203 = 3 ;  

.equ SEG204 = 4 ;  

.equ SEG205 = 5 ;  

.equ SEG206 = 6 ;  

.equ SEG207 = 7 ;  

 

; LCDDR8 - LCD Data Register 8 

.equ SEG124 = 0 ;  

 

; LCDDR7 - LCD Data Register 7 

.equ SEG116 = 0 ;  

.equ SEG117 = 1 ;  

.equ SEG118 = 2 ;  

.equ SEG119 = 3 ;  

.equ SEG120 = 4 ;  

.equ SEG121 = 5 ;  

.equ SEG122 = 6 ;  

.equ SEG123 = 7 ;  

 

; LCDDR6 - LCD Data Register 6 

.equ SEG108 = 0 ;  

.equ SEG109 = 1 ;  

.equ SEG110 = 2 ;  

.equ SEG111 = 3 ;  

.equ SEG112 = 4 ;  

.equ SEG113 = 5 ;  

.equ SEG114 = 6 ;  

.equ SEG115 = 7 ;  

 

; LCDDR5 - LCD Data Register 5 

.equ SEG100 = 0 ;  

.equ SEG101 = 1 ;  

.equ SEG102 = 2 ;  

.equ SEG103 = 3 ;  

.equ SEG104 = 4 ;  

.equ SEG105 = 5 ;  

.equ SEG106 = 6 ;  

.equ SEG107 = 7 ;  

 

; LCDDR3 - LCD Data Register 3 

.equ SEG024 = 0 ;  

 

; LCDDR2 - LCD Data Register 2 

.equ SEG016 = 0 ;  

.equ SEG017 = 1 ;  

.equ SEG018 = 2 ;  

.equ SEG019 = 3 ;  

.equ SEG020 = 4 ;  

.equ SEG021 = 5 ;  

.equ SEG022 = 6 ;  

.equ SEG023 = 7 ;  

 

; LCDDR1 - LCD Data Register 1 

.equ SEG008 = 0 ;  

.equ SEG009 = 1 ;  

.equ SEG010 = 2 ;  

.equ SEG011 = 3 ;  

.equ SEG012 = 4 ;  

.equ SEG013 = 5 ;  

.equ SEG014 = 6 ;  

.equ SEG015 = 7 ;  

 

; LCDDR0 - LCD Data Register 0 

.equ SEG000 = 0 ;  

.equ SEG001 = 1 ;  

.equ SEG002 = 2 ;  

.equ SEG003 = 3 ;  

.equ SEG004 = 4 ;  

.equ SEG005 = 5 ;  

.equ SEG006 = 6 ;  

.equ SEG007 = 7 ;  

 

 

; ***** EXTERNAL_INTERRUPT *********** 

; EICRA - External Interrupt Control Register 

.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 

.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 

 

; EIMSK - External Interrupt Mask Register 

.equ INT0 = 0 ; External Interrupt Request 0 Enable 

.equ PCIE0 = 6 ; Pin Change Interrupt Enable 0 

.equ PCIE1 = 7 ; Pin Change Interrupt Enable 1 

 

; EIFR - External Interrupt Flag Register 

.equ INTF0 = 0 ; External Interrupt Flag 0 

.equ PCIF0 = 6 ; Pin Change Interrupt Flag 0 

.equ PCIF1 = 7 ; Pin Change Interrupt Flag 1 

 

; PCMSK1 - Pin Change Mask Register 1 

.equ PCINT8 = 0 ; Pin Change Enable Mask 8 

.equ PCINT9 = 1 ; Pin Change Enable Mask 9 

.equ PCINT10 = 2 ; Pin Change Enable Mask 10 

.equ PCINT11 = 3 ; Pin Change Enable Mask 11 

.equ PCINT12 = 4 ; Pin Change Enable Mask 12 

.equ PCINT13 = 5 ; Pin Change Enable Mask 13 

.equ PCINT14 = 6 ; Pin Change Enable Mask 14 

.equ PCINT15 = 7 ; Pin Change Enable Mask 15 

 

; PCMSK0 - Pin Change Mask Register 0 

.equ PCINT0 = 0 ; Pin Change Enable Mask 0 

.equ PCINT1 = 1 ; Pin Change Enable Mask 1 

.equ PCINT2 = 2 ; Pin Change Enable Mask 2 

.equ PCINT3 = 3 ; Pin Change Enable Mask 3 

.equ PCINT4 = 4 ; Pin Change Enable Mask 4 

.equ PCINT5 = 5 ; Pin Change Enable Mask 5 

.equ PCINT6 = 6 ; Pin Change Enable Mask 6 

.equ PCINT7 = 7 ; Pin Change Enable Mask 7 

 

 

; ***** USI ************************** 

; USIDR - USI Data Register 

.equ USIDR0 = 0 ; USI Data Register bit 0 

.equ USIDR1 = 1 ; USI Data Register bit 1 

.equ USIDR2 = 2 ; USI Data Register bit 2 

.equ USIDR3 = 3 ; USI Data Register bit 3 

.equ USIDR4 = 4 ; USI Data Register bit 4 

.equ USIDR5 = 5 ; USI Data Register bit 5 

.equ USIDR6 = 6 ; USI Data Register bit 6 

.equ USIDR7 = 7 ; USI Data Register bit 7 

 

; USISR - USI Status Register 

.equ USICNT0 = 0 ; USI Counter Value Bit 0 

.equ USICNT1 = 1 ; USI Counter Value Bit 1 

.equ USICNT2 = 2 ; USI Counter Value Bit 2 

.equ USICNT3 = 3 ; USI Counter Value Bit 3 

.equ USIDC = 4 ; Data Output Collision 

.equ USIPF = 5 ; Stop Condition Flag 

.equ USIOIF = 6 ; Counter Overflow Interrupt Flag 

.equ USISIF = 7 ; Start Condition Interrupt Flag 

 

; USICR - USI Control Register 

.equ USITC = 0 ; Toggle Clock Port Pin 

.equ USICLK = 1 ; Clock Strobe 

.equ USICS0 = 2 ; USI Clock Source Select Bit 0 

.equ USICS1 = 3 ; USI Clock Source Select Bit 1 

.equ USIWM0 = 4 ; USI Wire Mode Bit 0 

.equ USIWM1 = 5 ; USI Wire Mode Bit 1 

.equ USIOIE = 6 ; Counter Overflow Interrupt Enable 

.equ USISIE = 7 ; Start Condition Interrupt Enable 

 

 

; ***** AD_CONVERTER ***************** 

; ADMUX - The ADC multiplexer Selection Register 

.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits 

.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits 

.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits 

.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits 

.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits 

.equ ADLAR = 5 ; Left Adjust Result 

.equ REFS0 = 6 ; Reference Selection Bit 0 

.equ REFS1 = 7 ; Reference Selection Bit 1 

 

; ADCSRA - The ADC Control and Status register 

.equ ADPS0 = 0 ; ADC  Prescaler Select Bits 

.equ ADPS1 = 1 ; ADC  Prescaler Select Bits 

.equ ADPS2 = 2 ; ADC  Prescaler Select Bits 

.equ ADIE = 3 ; ADC Interrupt Enable 

.equ ADIF = 4 ; ADC Interrupt Flag 

.equ ADATE = 5 ; ADC Auto Trigger Enable 

.equ ADSC = 6 ; ADC Start Conversion 

.equ ADEN = 7 ; ADC Enable 

 

; ADCH - ADC Data Register High Byte 

.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 

.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 

.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 

.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 

.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 

.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 

.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 

.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 

 

; ADCL - ADC Data Register Low Byte 

.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 

.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 

.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 

.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 

.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 

.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 

.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 

.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 

 

; ADCSRB - ADC Control and Status Register B 

.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 

.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 

.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 

 

; DIDR0 - Digital Input Disable Register 0 

.equ ADC0D = 0 ; ADC0 Digital input Disable 

.equ ADC1D = 1 ; ADC1 Digital input Disable 

.equ ADC2D = 2 ; ADC2 Digital input Disable 

.equ ADC3D = 3 ; ADC3 Digital input Disable 

.equ ADC4D = 4 ; ADC4 Digital input Disable 

.equ ADC5D = 5 ; ADC5 Digital input Disable 

.equ ADC6D = 6 ; ADC6 Digital input Disable 

.equ ADC7D = 7 ; ADC7 Digital input Disable 

 

 

; ***** BOOT_LOAD ******************** 

; SPMCSR - Store Program Memory Control Register 

.equ SPMCR = SPMCSR ; For compatibility 

.equ SPMEN = 0 ; Store Program Memory Enable 

.equ PGERS = 1 ; Page Erase 

.equ PGWRT = 2 ; Page Write 

.equ BLBSET = 3 ; Boot Lock Bit Set 

.equ RWWSRE = 4 ; Read While Write section read enable 

.equ ASRE = RWWSRE ; For compatibility 

.equ RWWSB = 6 ; Read While Write Section Busy 

.equ ASB = RWWSB ; For compatibility 

.equ SPMIE = 7 ; SPM Interrupt Enable 

 

 

; ***** USART0 *********************** 

; UDR0 - USART I/O Data Register 

.equ UDR = UDR0 ; For compatibility 

.equ UDR00 = 0 ; USART I/O Data Register bit 0 

.equ UDR01 = 1 ; USART I/O Data Register bit 1 

.equ UDR02 = 2 ; USART I/O Data Register bit 2 

.equ UDR03 = 3 ; USART I/O Data Register bit 3 

.equ UDR04 = 4 ; USART I/O Data Register bit 4 

.equ UDR05 = 5 ; USART I/O Data Register bit 5 

.equ UDR06 = 6 ; USART I/O Data Register bit 6 

.equ UDR07 = 7 ; USART I/O Data Register bit 7 

 

; UCSR0A - USART Control and Status Register A 

.equ UCSRA = UCSR0A ; For compatibility 

.equ USR = UCSR0A ; For compatibility 

.equ MPCM0 = 0 ; Multi-processor Communication Mode 

.equ MPCM = MPCM0 ; For compatibility 

.equ U2X0 = 1 ; Double the USART Transmission Speed 

.equ U2X = U2X0 ; For compatibility 

.equ UPE0 = 2 ; USART Parity Error 

.equ UPE = UPE0 ; For compatibility 

.equ DOR0 = 3 ; Data OverRun 

.equ DOR = DOR0 ; For compatibility 

.equ FE0 = 4 ; Framing Error 

.equ FE = FE0 ; For compatibility 

.equ UDRE0 = 5 ; USART Data Register Empty 

.equ UDRE = UDRE0 ; For compatibility 

.equ TXC0 = 6 ; USART Transmit Complete 

.equ TXC = TXC0 ; For compatibility 

.equ RXC0 = 7 ; USART Receive Complete 

.equ RXC = RXC0 ; For compatibility 

 

; UCSR0B - USART Control and Status Register B 

.equ UCSRB = UCSR0B ; For compatibility 

.equ UCR = UCSR0B ; For compatibility 

.equ TXB80 = 0 ; Transmit Data Bit 8 

.equ TXB8 = TXB80 ; For compatibility 

.equ RXB80 = 1 ; Receive Data Bit 8 

.equ RXB8 = RXB80 ; For compatibility 

.equ UCSZ02 = 2 ; Character Size 

.equ UCSZ2 = UCSZ02 ; For compatibility 

.equ TXEN0 = 3 ; Transmitter Enable 

.equ TXEN = TXEN0 ; For compatibility 

.equ RXEN0 = 4 ; Receiver Enable 

.equ RXEN = RXEN0 ; For compatibility 

.equ UDRIE0 = 5 ; USART Data Register Empty Interrupt Enable 

.equ UDRIE = UDRIE0 ; For compatibility 

.equ TXCIE0 = 6 ; TX Complete Interrupt Enable 

.equ TXCIE = TXCIE0 ; For compatibility 

.equ RXCIE0 = 7 ; RX Complete Interrupt Enable 

.equ RXCIE = RXCIE0 ; For compatibility 

 

; UCSR0C - USART Control and Status Register C 

.equ UCSRC = UCSR0C ; For compatibility 

.equ UCPOL0 = 0 ; Clock Polarity 

.equ UCPOL = UCPOL0 ; For compatibility 

.equ UCSZ00 = 1 ; Character Size 

.equ UCSZ0 = UCSZ00 ; For compatibility 

.equ UCSZ01 = 2 ; Character Size 

.equ UCSZ1 = UCSZ01 ; For compatibility 

.equ USBS0 = 3 ; Stop Bit Select 

.equ USBS = USBS0 ; For compatibility 

.equ UPM00 = 4 ; Parity Mode Bit 0 

.equ UPM0 = UPM00 ; For compatibility 

.equ UPM01 = 5 ; Parity Mode Bit 1 

.equ UPM1 = UPM01 ; For compatibility 

.equ UMSEL0 = 6 ; USART Mode Select 

.equ UMSEL = UMSEL0 ; For compatibility 

 

; UBRR0H - USART Baud Rate Register High Byte 

.equ UBRRH = UBRR0H ; For compatibility 

.equ UBRR_8 = 0 ; USART Baud Rate Register bit 8 

.equ UBRR_9 = 1 ; USART Baud Rate Register bit 9 

.equ UBRR_10 = 2 ; USART Baud Rate Register bit 10 

.equ UBRR_11 = 3 ; USART Baud Rate Register bit 11 

 

; UBRR0L - USART Baud Rate Register Low Byte 

.equ UBRRL = UBRR0L ; For compatibility 

.equ UBRR = UBRR0L ; For compatibility 

.equ UBRR_0 = 0 ; USART Baud Rate Register bit 0 

.equ UBRR_1 = 1 ; USART Baud Rate Register bit 1 

.equ UBRR_2 = 2 ; USART Baud Rate Register bit 2 

.equ UBRR_3 = 3 ; USART Baud Rate Register bit 3 

.equ UBRR_4 = 4 ; USART Baud Rate Register bit 4 

.equ UBRR_5 = 5 ; USART Baud Rate Register bit 5 

.equ UBRR_6 = 6 ; USART Baud Rate Register bit 6 

.equ UBRR_7 = 7 ; USART Baud Rate Register bit 7 

 

 

; ***** CPU ************************** 

; SREG - Status Register 

.equ SREG_C = 0 ; Carry Flag 

.equ SREG_Z = 1 ; Zero Flag 

.equ SREG_N = 2 ; Negative Flag 

.equ SREG_V = 3 ; Two's Complement Overflow Flag 

.equ SREG_S = 4 ; Sign Bit 

.equ SREG_H = 5 ; Half Carry Flag 

.equ SREG_T = 6 ; Bit Copy Storage 

.equ SREG_I = 7 ; Global Interrupt Enable 

 

; MCUCR - MCU Control Register 

.equ IVCE = 0 ; Interrupt Vector Change Enable 

.equ IVSEL = 1 ; Interrupt Vector Select 

.equ PUD = 4 ; Pull-up disable 

 

; MCUSR - MCU Status Register 

.equ PORF = 0 ; Power-on reset flag 

.equ EXTRF = 1 ; External Reset Flag 

.equ BORF = 2 ; Brown-out Reset Flag 

.equ WDRF = 3 ; Watchdog Reset Flag 

;.equ JTRF = 4 ; JTAG Reset Flag 

 

; OSCCAL - Oscillator Calibration Value 

.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 

.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 

.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 

.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 

.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 

.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 

.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 

.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 

 

; CLKPR - Clock Prescale Register 

.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 

.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 

.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 

.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 

.equ CLKPCE = 7 ; Clock Prescaler Change Enable 

 

; PRR - Power Reduction Register 

.equ PRADC = 0 ; Power Reduction ADC 

.equ PRUSART0 = 1 ; Power Reduction USART 

.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface 

.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 

.equ PRLCD = 4 ; Power Reduction LCD 

 

; SMCR - Sleep Mode Control Register 

.equ SE = 0 ; Sleep Enable 

.equ SM0 = 1 ; Sleep Mode Select bit 0 

.equ SM1 = 2 ; Sleep Mode Select bit 1 

.equ SM2 = 3 ; Sleep Mode Select bit 2 

 

; GPIOR2 - General Purpose IO Register 2 

.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 

.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 

.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 

.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 

.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 

.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 

.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 

.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 

 

; GPIOR1 - General Purpose IO Register 1 

.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 

.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 

.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 

.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 

.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 

.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 

.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 

.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 

 

; GPIOR0 - General Purpose IO Register 0 

.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 

.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 

.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 

.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 

.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 

.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 

.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 

.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 

 

 

; ***** PORTG ************************ 

; PORTG - Port G Data Register 

.equ PORTG0 = 0 ;  

.equ PG0 = 0 ; For compatibility 

.equ PORTG1 = 1 ;  

.equ PG1 = 1 ; For compatibility 

.equ PORTG2 = 2 ;  

.equ PG2 = 2 ; For compatibility 

.equ PORTG3 = 3 ;  

.equ PG3 = 3 ; For compatibility 

.equ PORTG4 = 4 ;  

.equ PG4 = 4 ; For compatibility 

.equ PORTG5 = 5 ;  

.equ PG5 = 5 ; For compatibility 

 

; DDRG - Port G Data Direction Register 

.equ DDG0 = 0 ;  

.equ DDG1 = 1 ;  

.equ DDG2 = 2 ;  

.equ DDG3 = 3 ;  

.equ DDG4 = 4 ;  

.equ DDG5 = 5 ;  

 

; PING - Port G Input Pins 

.equ PING0 = 0 ;  

.equ PING1 = 1 ;  

.equ PING2 = 2 ;  

.equ PING3 = 3 ;  

.equ PING4 = 4 ;  

.equ PING5 = 5 ;  

 

 

 

; ***** LOCKSBITS ******************************************************** 

.equ LB1 = 0 ; Lock bit 

.equ LB2 = 1 ; Lock bit 

.equ BLB01 = 2 ; Boot Lock bit 

.equ BLB02 = 3 ; Boot Lock bit 

.equ BLB11 = 4 ; Boot lock bit 

.equ BLB12 = 5 ; Boot lock bit 

 

 

; ***** FUSES ************************************************************ 

; LOW fuse bits 

.equ CKSEL0 = 0 ; Select Clock Source 

.equ CKSEL1 = 1 ; Select Clock Source 

.equ CKSEL2 = 2 ; Select Clock Source 

.equ CKSEL3 = 3 ; Select Clock Source 

.equ SUT0 = 4 ; Select start-up time 

.equ SUT1 = 5 ; Select start-up time 

.equ CKOUT = 6 ; Oscillator options 

.equ CKDIV8 = 7 ; Divide clock by 8 

 

; HIGH fuse bits 

.equ BOOTRST = 0 ; Select Reset Vector 

.equ BOOTSZ0 = 1 ; Select Boot Size 

.equ BOOTSZ1 = 2 ; Select Boot Size 

.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase 

.equ WDTON = 4 ; Watchdog timer always on 

.equ SPIEN = 5 ; Enable Serial programming and Data Downloading 

.equ JTAGEN = 6 ; Enable JTAG 

.equ OCDEN = 7 ; Enable OCD 

 

; EXTENDED fuse bits 

.equ RSTDISBL = 0 ; Disable external reset 

.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level 

.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level 

.equ BODLEVEL2 = 3 ; Brown out detector trigger level 

 

 

 

; ***** CPU REGISTER DEFINITIONS ***************************************** 

.def XH = r27 

.def XL = r26 

.def YH = r29 

.def YL = r28 

.def ZH = r31 

.def ZL = r30 

 

 

 

; ***** DATA MEMORY DECLARATIONS ***************************************** 

.equ FLASHEND = 0x1fff ; Note: Word address 

.equ IOEND = 0x00ff 

.equ SRAM_START = 0x0100 

.equ SRAM_SIZE = 1024 

.equ RAMEND = 0x04ff 

.equ XRAMEND = 0x0000 

.equ E2END = 0x01ff 

.equ EEPROMEND = 0x01ff 

.equ EEADRBITS = 9 

#pragma AVRPART MEMORY PROG_FLASH 16384 

#pragma AVRPART MEMORY EEPROM 512 

#pragma AVRPART MEMORY INT_SRAM SIZE 1024 

#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 

 

 

 

; ***** BOOTLOADER DECLARATIONS ****************************************** 

.equ NRWW_START_ADDR = 0x1c00 

.equ NRWW_STOP_ADDR = 0x1fff 

.equ RWW_START_ADDR = 0x0 

.equ RWW_STOP_ADDR = 0x1bff 

.equ PAGESIZE = 64 

.equ FIRSTBOOTSTART = 0x1f80 

.equ SECONDBOOTSTART = 0x1f00 

.equ THIRDBOOTSTART = 0x1e00 

.equ FOURTHBOOTSTART = 0x1c00 

.equ SMALLBOOTSTART = FIRSTBOOTSTART 

.equ LARGEBOOTSTART = FOURTHBOOTSTART 

 

 

 

; ***** INTERRUPT VECTORS ************************************************ 

.equ INT0addr = 0x0002 ; External Interrupt Request 0 

.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0 

.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1 

.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match 

.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow 

.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event 

.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A 

.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B 

.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow 

.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match 

.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow 

.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete 

.equ URXC0addr = 0x001a ; USART0, Rx Complete 

.equ URXCaddr = 0x001a ; For compatibility 

.equ UDRE0addr = 0x001c ; USART0 Data register Empty 

.equ UDREaddr = 0x001c ; For compatibility 

.equ UTXC0addr = 0x001e ; USART0, Tx Complete 

.equ UTXCaddr = 0x001e ; For compatibility 

.equ USI_STARTaddr = 0x0020 ; USI Start Condition 

.equ USI_OVFaddr = 0x0022 ; USI Overflow 

.equ ACIaddr = 0x0024 ; Analog Comparator 

.equ ADCCaddr = 0x0026 ; ADC Conversion Complete 

.equ ERDYaddr = 0x0028 ; EEPROM Ready 

.equ SPMRaddr = 0x002a ; Store Program Memory Read 

.equ LCDSFaddr = 0x002c ; LCD Start of Frame 

 

.equ INT_VECTORS_SIZE = 46 ; size in words 

 

#endif  /* _M169PDEF_INC_ */ 

 

; ***** END OF FILE ******************************************************

Iom169.h listing

iom169.h listing, click to expand

/* Copyright (c) 2002, 2003, 2004, 2005  

   Juergen Schilling <juergen.schilling@honeywell.com> 

   Eric B. Weddington 

   All rights reserved. 

 

   Redistribution and use in source and binary forms, with or without 

   modification, are permitted provided that the following conditions are met: 

 

   * Redistributions of source code must retain the above copyright 

     notice, this list of conditions and the following disclaimer. 

 

   * Redistributions in binary form must reproduce the above copyright 

     notice, this list of conditions and the following disclaimer in 

     the documentation and/or other materials provided with the 

     distribution. 

 

   * Neither the name of the copyright holders nor the names of 

     contributors may be used to endorse or promote products derived 

     from this software without specific prior written permission. 

 

  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 

  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 

  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 

  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 

  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 

  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 

  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 

  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 

  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 

  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 

  POSSIBILITY OF SUCH DAMAGE. */ 

 

/* $Id: iom169.h 1873 2009-02-11 17:53:39Z arcanum $ */ 

 

/* iom169.h - definitions for ATmega169 */ 

 

/* This should be up to date with data sheet version 2514J-AVR-12/03. */ 

 

#ifndef _AVR_IOM169_H_ 

#define _AVR_IOM169_H_ 1 

 

/* This file should only be included from <avr/io.h>, never directly. */ 

 

#ifndef _AVR_IO_H_ 

#  error "Include <avr/io.h> instead of this file." 

#endif 

 

#ifndef _AVR_IOXXX_H_ 

#  define _AVR_IOXXX_H_ "iom169.h" 

#else 

#  error "Attempt to include more than one <avr/ioXXX.h> file." 

#endif  

 

/* I/O registers */ 

 

/* Port A */ 

#define PINA   _SFR_IO8(0x00) 

#define DDRA   _SFR_IO8(0x01) 

#define PORTA  _SFR_IO8(0x02) 

 

/* Port B */ 

#define PINB   _SFR_IO8(0x03) 

#define DDRB   _SFR_IO8(0x04) 

#define PORTB  _SFR_IO8(0x05) 

 

/* Port C */ 

#define PINC   _SFR_IO8(0x06) 

#define DDRC   _SFR_IO8(0x07) 

#define PORTC  _SFR_IO8(0x08) 

 

/* Port D */ 

#define PIND   _SFR_IO8(0x09) 

#define DDRD   _SFR_IO8(0x0A) 

#define PORTD  _SFR_IO8(0x0B) 

 

/* Port E */ 

#define PINE   _SFR_IO8(0x0C) 

#define DDRE   _SFR_IO8(0x0D) 

#define PORTE  _SFR_IO8(0x0E) 

 

/* Port F */ 

#define PINF   _SFR_IO8(0x0F) 

#define DDRF   _SFR_IO8(0x10) 

#define PORTF  _SFR_IO8(0x11) 

 

/* Port G */ 

#define PING   _SFR_IO8(0x12) 

#define DDRG   _SFR_IO8(0x13) 

#define PORTG  _SFR_IO8(0x14) 

 

/* Timer/Counter 0 interrupt Flag Register */ 

#define TIFR0  _SFR_IO8(0x15) 

 

/* Timer/Counter 1 interrupt Flag Register */ 

#define TIFR1  _SFR_IO8(0x16) 

 

/* Timer/Counter 2 interrupt Flag Register */ 

#define TIFR2  _SFR_IO8(0x17) 

 

/* External Interrupt Flag Register */ 

#define EIFR   _SFR_IO8(0x1C) 

 

/* External Interrupt Mask Register */ 

#define EIMSK  _SFR_IO8(0x1D) 

 

/* General Purpose I/O Register 0 */ 

#define GPIOR0 _SFR_IO8(0x1E) 

 

#define EECR   _SFR_IO8(0x1F) 

 

#define EEDR   _SFR_IO8(0X20) 

 

/* Combine EEARL and EEARH */ 

#define EEAR   _SFR_IO16(0x21) 

#define EEARL  _SFR_IO8(0x21) 

#define EEARH  _SFR_IO8(0X22) 

 

/* 6-char sequence denoting where to find the EEPROM registers in memory space. 

   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM 

   subroutines. 

   First two letters:  EECR address. 

   Second two letters: EEDR address. 

   Last two letters:   EEAR address.  */ 

#define __EEPROM_REG_LOCATIONS__ 1F2021 

 

/* General Timer/Counter Control Register */ 

#define GTCCR  _SFR_IO8(0x23) 

 

/* Timer/Counter Control Register A */ 

#define TCCR0A _SFR_IO8(0x24) 

 

/* Timer/Counter Register */ 

#define TCNT0  _SFR_IO8(0x26) 

 

/* Output Compare Register A */ 

#define OCR0A  _SFR_IO8(0x27) 

 

/* General Purpose I/O Register 1 */ 

#define GPIOR1 _SFR_IO8(0x2A) 

 

/* General Purpose I/O Register 2 */ 

#define GPIOR2 _SFR_IO8(0x2B) 

 

/* SPI Control Register */ 

#define SPCR   _SFR_IO8(0x2C) 

 

/* SPI Status Register */ 

#define SPSR   _SFR_IO8(0x2D) 

 

/* SPI Data Register */ 

#define SPDR   _SFR_IO8(0x2E) 

 

/* Analog Comperator Control and Status Register */ 

#define ACSR   _SFR_IO8(0x30) 

 

/* On-chip Debug Register */ 

#define OCDR   _SFR_IO8(0x31) 

 

/* Sleep Mode Control Register */ 

#define SMCR   _SFR_IO8(0x33) 

 

/* MCU Status Register */ 

#define MCUSR  _SFR_IO8(0x34) 

 

/* MCU Control Rgeister */ 

#define MCUCR  _SFR_IO8(0x35) 

 

/* Store Program Memory Control and Status Register */ 

#define SPMCSR _SFR_IO8(0x37) 

 

/* Watchdog Timer Control Register */ 

#define WDTCR  _SFR_MEM8(0x60) 

 

/* Clock Prescale Register */ 

#define CLKPR  _SFR_MEM8(0x61) 

 

#define PRR    _SFR_MEM8(0x64) 

#define PRADC       0 

#define PRUSART0    1 

#define PRSPI       2 

#define PRTIM1      3 

#define PRLCD       4 

 

/* Oscillator Calibration Register */ 

#define OSCCAL _SFR_MEM8(0x66) 

 

/* External Interrupt Control Register A */ 

#define EICRA  _SFR_MEM8(0x69) 

 

/* Pin Change Mask Register */ 

#define PCMSK  _SFR_MEM16(0x6B) 

#define PCMSK0 _SFR_MEM8(0x6B) 

#define PCMSK1 _SFR_MEM8(0x6C) 

 

/* Timer/Counter 0 Interrupt Mask Register */ 

#define TIMSK0 _SFR_MEM8(0x6E) 

 

/* Timer/Counter 1 Interrupt Mask Register */ 

#define TIMSK1 _SFR_MEM8(0x6F) 

 

/* Timer/Counter 2 Interrupt Mask Register */ 

#define TIMSK2 _SFR_MEM8(0x70) 

 

/* ADC Data Register */ 

#ifndef __ASSEMBLER__ 

#define ADC    _SFR_MEM16(0x78) 

#endif 

#define ADCW   _SFR_MEM16(0x78) 

#define ADCL   _SFR_MEM8(0x78) 

#define ADCH   _SFR_MEM8(0x79) 

 

/* ADC Control and Status Register A */ 

#define ADCSRA _SFR_MEM8(0x7A) 

 

/* ADC Control and Status Register B */ 

#define ADCSRB _SFR_MEM8(0x7B) 

 

/* ADC Multiplex Selection Register */ 

#define ADMUX  _SFR_MEM8(0x7C) 

 

/* NOTE: DIDR0 and DIDR1 are swapped in the register summary of the data sheet 

   (2514D-AVR-01/03), but seem to be correct in the discussions of the 

   registers. */ 

 

/* Digital Input Disable Register 0 */ 

#define DIDR0  _SFR_MEM8(0x7E) 

 

/* Digital Input Disable Register 1 */ 

#define DIDR1  _SFR_MEM8(0x7F) 

 

/* Timer/Counter1 Control Register A */ 

#define TCCR1A _SFR_MEM8(0x80) 

 

/* Timer/Counter1 Control Register B */ 

#define TCCR1B _SFR_MEM8(0x81) 

 

/* Timer/Counter1 Control Register C */ 

#define TCCR1C _SFR_MEM8(0x82) 

 

/* Timer/Counter1 Register */ 

#define TCNT1  _SFR_MEM16(0x84) 

#define TCNT1L _SFR_MEM8(0x84) 

#define TCNT1H _SFR_MEM8(0x85) 

 

/* Timer/Counter1 Input Capture Register */ 

#define ICR1   _SFR_MEM16(0x86) 

#define ICR1L  _SFR_MEM8(0x86) 

#define ICR1H  _SFR_MEM8(0x87) 

 

/* Timer/Counter1 Output Compare Register A */ 

#define OCR1A  _SFR_MEM16(0x88) 

#define OCR1AL _SFR_MEM8(0x88) 

#define OCR1AH _SFR_MEM8(0x89) 

 

/* Timer/Counter1 Output Compare Registare B */ 

#define OCR1B  _SFR_MEM16(0x8A) 

#define OCR1BL _SFR_MEM8(0x8A) 

#define OCR1BH _SFR_MEM8(0x8B) 

 

/* Timer/Counter2 Control Register A */ 

#define TCCR2A _SFR_MEM8(0xB0) 

 

/* Timer/Counter2 Register */ 

#define TCNT2  _SFR_MEM8(0xB2) 

 

/* Timer/Counter2 Output Compare Register */ 

#define OCR2A  _SFR_MEM8(0xB3) 

 

/* Asynchronous Status Register */ 

#define ASSR   _SFR_MEM8(0xB6) 

 

/* USI Control Register */ 

#define USICR  _SFR_MEM8(0xB8) 

 

/* USI Status Register */ 

#define USISR  _SFR_MEM8(0xB9) 

 

/* USI Data Register */ 

#define USIDR  _SFR_MEM8(0xBA) 

 

/* USART0 Control and Status Register A */ 

#define UCSRA  _SFR_MEM8(0xC0) 

 

/* USART0 Control and Status Register B */ 

#define UCSRB  _SFR_MEM8(0xC1) 

 

/* USART0 Control and Status Register C */ 

#define UCSRC  _SFR_MEM8(0xC2) 

 

/* USART0 Baud Rate Register */ 

#define UBRR   _SFR_MEM16(0xC4) 

#define UBRRL  _SFR_MEM8(0xC4) 

#define UBRRH  _SFR_MEM8(0xC5) 

 

/* USART0 I/O Data Register */ 

#define UDR    _SFR_MEM8(0xC6) 

 

/* LCD Control and Status Register A */ 

#define LCDCRA _SFR_MEM8(0xE4) 

 

/* LCD Control and Status Register B */ 

#define LCDCRB _SFR_MEM8(0xE5) 

 

/* LCD Frame Rate Register */ 

#define LCDFRR _SFR_MEM8(0xE6) 

 

/* LCD Contrast Control Register */ 

#define LCDCCR _SFR_MEM8(0xE7) 

 

/* LCD Memory mapping */ 

#define LCDDR0 _SFR_MEM8(0xEC) 

#define LCDDR1 _SFR_MEM8(0xED) 

#define LCDDR2 _SFR_MEM8(0xEE) 

#define LCDDR3 _SFR_MEM8(0xEF) 

#define LCDDR5 _SFR_MEM8(0xF1) 

#define LCDDR6 _SFR_MEM8(0xF2) 

#define LCDDR7 _SFR_MEM8(0xF3) 

#define LCDDR8 _SFR_MEM8(0xF4) 

#define LCDDR10 _SFR_MEM8(0xF6) 

#define LCDDR11 _SFR_MEM8(0xF7) 

#define LCDDR12 _SFR_MEM8(0xF8) 

#define LCDDR13 _SFR_MEM8(0xF9) 

#define LCDDR15 _SFR_MEM8(0xFB) 

#define LCDDR16 _SFR_MEM8(0xFC) 

#define LCDDR17 _SFR_MEM8(0xFD) 

#define LCDDR18 _SFR_MEM8(0xFE) 

 

/* Interrupt vectors */ 

 

/* External Interrupt Request 0 */ 

#define INT0_vect _VECTOR(1) 

#define SIG_INTERRUPT0 _VECTOR(1) 

 

/* Pin Change Interrupt Request 0 */ 

#define PCINT0_vect _VECTOR(2) 

#define SIG_PIN_CHANGE0 _VECTOR(2) 

 

/* Pin Change Interrupt Request 1 */ 

#define PCINT1_vect _VECTOR(3) 

#define SIG_PIN_CHANGE1 _VECTOR(3) 

 

/* Timer/Counter2 Compare Match */ 

#define TIMER2_COMP_vect _VECTOR(4) 

#define SIG_OUTPUT_COMPARE2 _VECTOR(4) 

 

/* Timer/Counter2 Overflow */ 

#define TIMER2_OVF_vect _VECTOR(5) 

#define SIG_OVERFLOW2 _VECTOR(5) 

 

/* Timer/Counter1 Capture Event */ 

#define TIMER1_CAPT_vect _VECTOR(6) 

#define SIG_INPUT_CAPTURE1 _VECTOR(6) 

 

/* Timer/Counter1 Compare Match A */ 

#define TIMER1_COMPA_vect _VECTOR(7) 

#define SIG_OUTPUT_COMPARE1A _VECTOR(7) 

 

/* Timer/Counter Compare Match B */ 

#define TIMER1_COMPB_vect _VECTOR(8) 

#define SIG_OUTPUT_COMPARE1B _VECTOR(8) 

 

/* Timer/Counter1 Overflow */ 

#define TIMER1_OVF_vect _VECTOR(9) 

#define SIG_OVERFLOW1 _VECTOR(9) 

 

/* Timer/Counter0 Compare Match */ 

#define TIMER0_COMP_vect _VECTOR(10) 

#define SIG_OUTPUT_COMPARE0 _VECTOR(10) 

 

/* Timer/Counter0 Overflow */ 

#define TIMER0_OVF_vect _VECTOR(11) 

#define SIG_OVERFLOW0 _VECTOR(11) 

 

/* SPI Serial Transfer Complete */ 

#define SPI_STC_vect _VECTOR(12) 

#define SIG_SPI _VECTOR(12) 

 

/* USART0, Rx Complete */ 

#define USART0_RX_vect _VECTOR(13) 

#define SIG_USART_RECV _VECTOR(13) 

 

/* USART0 Data register Empty */ 

#define USART0_UDRE_vect _VECTOR(14) 

#define SIG_USART_DATA _VECTOR(14) 

 

/* USART0, Tx Complete */ 

#define USART0_TX_vect _VECTOR(15) 

#define SIG_USART_TRANS _VECTOR(15) 

 

/* USI Start Condition */ 

#define USI_START_vect _VECTOR(16) 

#define SIG_USI_START _VECTOR(16) 

 

/* USI Overflow */ 

#define USI_OVERFLOW_vect _VECTOR(17) 

#define SIG_USI_OVERFLOW _VECTOR(17) 

 

/* Analog Comparator */ 

#define ANALOG_COMP_vect _VECTOR(18) 

#define SIG_COMPARATOR _VECTOR(18) 

 

/* ADC Conversion Complete */ 

#define ADC_vect _VECTOR(19) 

#define SIG_ADC _VECTOR(19) 

 

/* EEPROM Ready */ 

#define EE_READY_vect _VECTOR(20) 

#define SIG_EEPROM_READY _VECTOR(20) 

 

/* Store Program Memory Read */ 

#define SPM_READY_vect _VECTOR(21) 

#define SIG_SPM_READY _VECTOR(21) 

 

/* LCD Start of Frame */ 

#define LCD_vect _VECTOR(22) 

#define SIG_LCD _VECTOR(22) 

 

#define _VECTORS_SIZE 92 

 

/* Bit numbers */ 

 

/* 

   PA7 = SEG3 

   PA6 = SEG2 

   PA5 = SEG1 

   PA4 = SEG0 

   PA3 = COM3 

   PA2 = COM2 

   PA1 = COM1 

   PA0 = COM0 

*/ 

 

/* PORTA */ 

#define PA7 7 

#define PA6 6 

#define PA5 5 

#define PA4 4 

#define PA3 3 

#define PA2 2 

#define PA1 1 

#define PA0 0 

 

/* DDRA */ 

#define DDA7 7 

#define DDA6 6 

#define DDA5 5 

#define DDA4 4 

#define DDA3 3 

#define DDA2 2 

#define DDA1 1 

#define DDA0 0 

 

/* PINA */ 

#define PINA7 7 

#define PINA6 6 

#define PINA5 5 

#define PINA4 4 

#define PINA3 3 

#define PINA2 2 

#define PINA1 1 

#define PINA0 0 

 

/* 

   PB7 = OC2A / PCINT15 

   PB6 = OC1B / PCINT14 

   PB5 = OC1A / PCINT13 

   PB4 = OC0A / PCINT12 

   PB3 = MISO / PCINT11 

   PB2 = MOSI / PCINT10 

   PB1 = SCK / PCINT9 

   PB0 = SS# / PCINT8 

 */ 

 

/* PORTB */ 

#define PB7 7 

#define PB6 6 

#define PB5 5 

#define PB4 4 

#define PB3 3 

#define PB2 2 

#define PB1 1 

#define PB0 0 

 

/* DDRB */ 

#define DDB7 7 

#define DDB6 6 

#define DDB5 5 

#define DDB4 4 

#define DDB3 3 

#define DDB2 2 

#define DDB1 1 

#define DDB0 0 

 

/* PINB */ 

#define PINB7 7 

#define PINB6 6 

#define PINB5 5 

#define PINB4 4 

#define PINB3 3 

#define PINB2 2 

#define PINB1 1 

#define PINB0 0 

 

/* 

   PC7 = SEG5 

   PC6 = SEG6 

   PC5 = SEG7 

   PC4 = SEG8 

   PC3 = SEG9 

   PC2 = SEG10 

   PC1 = SEG11 

   PC0 = SEG12 

*/ 

 

/* PORTC */ 

#define PC7 7 

#define PC6 6 

#define PC5 5 

#define PC4 4 

#define PC3 3 

#define PC2 2 

#define PC1 1 

#define PC0 0 

 

/* DDRC */ 

#define DDC7 7 

#define DDC6 6 

#define DDC5 5 

#define DDC4 4 

#define DDC3 3 

#define DDC2 2 

#define DDC1 1 

#define DDC0 0 

 

/* PINC */ 

#define PINC7 7 

#define PINC6 6 

#define PINC5 5 

#define PINC4 4 

#define PINC3 3 

#define PINC2 2 

#define PINC1 1 

#define PINC0 0 

 

/* 

   PD7 = SEG15 

   PD6 = SEG16 

   PD5 = SEG17 

   PD4 = SEG18 

   PD3 = SEG19 

   PD2 = SEG20 

   PD1 = INT0 / SEG21 

   PD0 = ICP / SEG22 

 */ 

 

/* PORTD */ 

#define PD7 7 

#define PD6 6 

#define PD5 5 

#define PD4 4 

#define PD3 3 

#define PD2 2 

#define PD1 1 

#define PD0 0 

 

/* DDRD */ 

#define DDD7 7 

#define DDD6 6 

#define DDD5 5 

#define DDD4 4 

#define DDD3 3 

#define DDD2 2 

#define DDD1 1 

#define DDD0 0 

 

/* PIND */ 

#define PIND7 7 

#define PIND6 6 

#define PIND5 5 

#define PIND4 4 

#define PIND3 3 

#define PIND2 2 

#define PIND1 1 

#define PIND0 0 

 

/* 

   PE7 = CLK0 / PCINT7 

   PE6 = DO / PCINT6 

   PE5 = DI / SDA / PCINT5 

   PE4 = USCK / SCL / PCINT4 

   PE3 = AIN1 / PCINT3 

   PE2 = XCK / AIN0 / PCINT2 

   PE1 = TXD / PCINT1 

   PE0 = RXD / PCINT0 

 */ 

 

/* PORTE */ 

#define PE7 7 

#define PE6 6 

#define PE5 5 

#define PE4 4 

#define PE3 3 

#define PE2 2 

#define PE1 1 

#define PE0 0 

 

/* DDRE */ 

#define DDE7 7 

#define DDE6 6 

#define DDE5 5 

#define DDE4 4 

#define DDE3 3 

#define DDE2 2 

#define DDE1 1 

#define DDE0 0 

 

/* PINE */ 

#define PINE7 7 

#define PINE6 6 

#define PINE5 5 

#define PINE4 4 

#define PINE3 3 

#define PINE2 2 

#define PINE1 1 

#define PINE0 0 

 

/* 

   PF7 = ADC7 / TDI 

   PF6 = ADC6 / TDO 

   PF5 = ADC5 / TMS 

   PF4 = ADC4 / TCK 

   PF3 = ADC3 

   PF2 = ADC2 

   PF1 = ADC1 

   PF0 = ADC0 

 */ 

 

/* PORTF */ 

#define PF7 7 

#define PF6 6 

#define PF5 5 

#define PF4 4 

#define PF3 3 

#define PF2 2 

#define PF1 1 

#define PF0 0 

 

/* DDRF */ 

#define DDF7 7 

#define DDF6 6 

#define DDF5 5 

#define DDF4 4 

#define DDF3 3 

#define DDF2 2 

#define DDF1 1 

#define DDF0 0 

 

/* PINF */ 

#define PINF7 7 

#define PINF6 6 

#define PINF5 5 

#define PINF4 4 

#define PINF3 3 

#define PINF2 2 

#define PINF1 1 

#define PINF0 0 

 

/* 

   PG5 = RESET# 

   PG4 = T0 / SEG23 

   PG3 = T1 / SEG24 

   PG2 = SEG4 

   PG1 = SEG13 

   PG0 = SEG14 

 */ 

 

/* PORTG */ 

#define PG4 4 

#define PG3 3 

#define PG2 2 

#define PG1 1 

#define PG0 0 

 

/* DDRG */ 

#define DDG4 4 

#define DDG3 3 

#define DDG2 2 

#define DDG1 1 

#define DDG0 0 

 

/* PING */ 

#define PING5 5 

#define PING4 4 

#define PING3 3 

#define PING2 2 

#define PING1 1 

#define PING0 0 

 

/* TIFR0 */ 

#define OCF0A 1 

#define TOV0 0 

 

/* TIFR1 */ 

#define ICF1   5 

#define OCF1B  2 

#define OCF1A 1 

#define TOV1 0 

 

/* TIFR2 */ 

#define OCF2A 1 

#define TOV2 0 

 

/* EIFR */ 

#define PCIF1  7 

#define PCIF0  6 

#define INTF0  0 

 

/* EIMSK */ 

#define PCIE1  7 

#define PCIE0  6 

#define INT0   0 

 

/* EECR */ 

#define EERIE   3 

#define EEMWE   2 

#define EEWE    1 

#define EERE    0 

 

/* GTCCR */ 

#define TSM    7 

#define PSR2   1 

#define PSR10  0 

 

/* TCCR0A */ 

#define FOC0A 7 

#define WGM00 6 

#define COM0A1 5 

#define COM0A0 4 

#define WGM01 3 

#define CS02 2 

#define CS01 1 

#define CS00 0 

 

/* SPCR */ 

#define SPIE 7 

#define SPE    6 

#define DORD 5 

#define MSTR 4 

#define CPOL 3 

#define CPHA 2 

#define SPR1 1 

#define SPR0 0 

 

/* SPSR */ 

#define SPIF 7 

#define WCOL 6 

#define SPI2X 0 

 

/* ACSR */ 

#define ACD    7 

#define ACBG 6 

#define ACO    5 

#define ACI    4 

#define ACIE 3 

#define ACIC 2 

#define ACIS1 1 

#define ACIS0 0 

 

/* OCDR */ 

#define IDRD   7 

#define OCD    7 

#define OCDR6  6 

#define OCDR5  5 

#define OCDR4  4 

#define OCDR3  3 

#define OCDR2  2 

#define OCDR1  1 

#define OCDR0  0 

 

/* SMCR */ 

#define SM2    3 

#define SM1    2 

#define SM0    1 

#define SE     0 

 

/* MCUSR */ 

#define JTRF   4 

#define WDRF   3 

#define BORF   2 

#define EXTRF  1 

#define PORF   0 

 

/* MCUCR */ 

#define JTD    7 

#define PUD    4 

#define IVSEL  1 

#define IVCE   0 

 

/* SPMCSR */ 

#define SPMIE  7 

#define RWWSB  6 

#define RWWSRE 4 

#define BLBSET 3 

#define PGWRT  2 

#define PGERS  1 

#define SPMEN  0 

 

/* WDTCR */ 

#define WDCE 4 

#define WDE    3 

#define WDP2 2 

#define WDP1 1 

#define WDP0 0 

 

/* CLKPR */ 

#define CLKPCE 7 

#define CLKPS3 3 

#define CLKPS2 2 

#define CLKPS1 1 

#define CLKPS0 0 

 

/* EICRA */ 

#define ISC01  1 

#define ISC00  0 

 

/* PCMSK0 */ 

#define PCINT7 7 

#define PCINT6 6 

#define PCINT5 5 

#define PCINT4 4 

#define PCINT3 3 

#define PCINT2 2 

#define PCINT1 1 

#define PCINT0 0 

 

/* PCMSK1 */ 

#define PCINT15 7 

#define PCINT14 6 

#define PCINT13 5 

#define PCINT12 4 

#define PCINT11 3 

#define PCINT10 2 

#define PCINT9 1 

#define PCINT8 0 

 

/* TIMSK0 */ 

#define OCIE0A 1 

#define TOIE0  0 

 

/* TIMSK1 */ 

#define ICIE1  5 

#define OCIE1B 2 

#define OCIE1A 1 

#define TOIE1  0 

 

/* TIMSK2 */ 

#define OCIE2A 1 

#define TOIE2  0 

 

/* ADCSRA */ 

#define ADEN   7 

#define ADSC   6 

#define ADATE  5 

#define ADIF   4 

#define ADIE   3 

#define ADPS2  2 

#define ADPS1  1 

#define ADPS0  0 

 

/* ADCSRB */ 

#define ACME   6 

#define ADTS2  2 

#define ADTS1  1 

#define ADTS0  0 

 

/* ADMUX */ 

#define REFS1  7 

#define REFS0  6 

#define ADLAR  5 

#define MUX4   4 

#define MUX3   3 

#define MUX2   2 

#define MUX1   1 

#define MUX0   0 

 

/* DIDR1 */ 

#define AIN1D  1 

#define AIN0D  0 

 

/* DIDR0 */ 

#define ADC7D  7 

#define ADC6D  6 

#define ADC5D  5 

#define ADC4D  4 

#define ADC3D  3 

#define ADC2D  2 

#define ADC1D  1 

#define ADC0D  0 

 

/* TCCR1A */ 

#define COM1A1 7 

#define COM1A0 6 

#define COM1B1 5 

#define COM1B0 4 

#define WGM11 1 

#define WGM10 0 

 

/* TCCR1B */ 

#define ICNC1 7 

#define ICES1 6 

#define WGM13  4 

#define WGM12 3 

#define CS12 2 

#define CS11 1 

#define CS10 0 

 

/* TCCR1C */ 

#define FOC1A  7 

#define FOC1B  6 

 

/* TCCR2A */ 

#define FOC2A 7 

#define WGM20 6 

#define COM2A1 5 

#define COM2A0 4 

#define WGM21 3 

#define CS22 2 

#define CS21 1 

#define CS20 0 

 

/* ASSR */ 

#define EXCLK  4 

#define AS2    3 

#define TCN2UB 2 

#define OCR2UB 1 

#define TCR2UB 0 

 

/* USICR */ 

#define USISIE 7 

#define USIOIE 6 

#define USIWM1 5 

#define USIWM0 4 

#define USICS1 3 

#define USICS0 2 

#define USICLK 1 

#define USITC  0 

 

/* USISR */ 

#define USISIF 7 

#define USIOIF 6 

#define USIPF  5 

#define USIDC  4 

#define USICNT3 3 

#define USICNT2 2 

#define USICNT1 1 

#define USICNT0 0 

 

/* UCSRA */ 

#define RXC 7 

#define TXC 6 

#define UDRE 5 

#define FE 4 

#define DOR 3 

#define UPE 2 

#define U2X     1 

#define MPCM 0 

 

/* UCSRB */ 

#define RXCIE 7 

#define TXCIE 6 

#define UDRIE 5 

#define RXEN 4 

#define TXEN 3 

#define UCSZ2   2 

#define RXB8 1 

#define TXB8 0  
#define LCDIF  4 

#define LCDIE  3 

#define LCDBD  2 /* Only in Rev. F */ 

#define LCDCCD 1 /* Only in Rev. F */ 

#define LCDBL  0 

 

/* LCDCRB */ 

#define LCDCS  7 

#define LCD2B  6 

#define LCDMUX1 5 

#define LCDMUX0 4 

#define LCDPM2 2 

#define LCDPM1 1 

#define LCDPM0 0 

 

/* LCDFRR */ 

#define LCDPS2 6 

#define LCDPS1 5 

#define LCDPS0 4 

#define LCDCD2 2 

#define LCDCD1 1 

#define LCDCD0 0 

 

/* LCDCCR */ 

#define LCDDC2 7 

#define LCDDC1 6 

#define LCDDC0 5 

#define LCDMDT 4 /* Only in Rev. F */ 

#define LCDCC3 3 

#define LCDCC2 2 

#define LCDCC1 1 

#define LCDCC0 0 

 

/* LCDDR0-18 */ 

#define SEG24  0 

 

#define SEG23  7 

#define SEG22  6 

#define SEG21  5 

#define SEG20  4 

#define SEG19  3 

#define SEG18  2 

#define SEG17  1 

#define SEG16  0 

 

#define SEG15  7 

#define SEG14  6 

#define SEG5   5 

#define SEG4   4 

#define SEG3   3 

#define SEG2   2 

#define SEG1   1 

#define SEG0   0 

 

/* Constants */ 

#define SPM_PAGESIZE 128 

#define RAMEND 0x4FF 

#define XRAMEND RAMEND 

#define E2END 0x1FF 

#define E2PAGESIZE  4 

#define FLASHEND 0x3FFF 

 

 

/* Fuses */ 

 

#define FUSE_MEMORY_SIZE 3 

 

/* Low Fuse Byte */ 

#define FUSE_CKSEL0      (unsigned char)~_BV(0) 

#define FUSE_CKSEL1      (unsigned char)~_BV(1) 

#define FUSE_CKSEL2      (unsigned char)~_BV(2) 

#define FUSE_CKSEL3      (unsigned char)~_BV(3) 

#define FUSE_SUT0        (unsigned char)~_BV(4) 

#define FUSE_SUT1        (unsigned char)~_BV(5) 

#define FUSE_CKOUT       (unsigned char)~_BV(6) 

#define FUSE_CKDIV8      (unsigned char)~_BV(7) 

#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) 

 

/* High Fuse Byte */ 

#define FUSE_BOOTRST     (unsigned char)~_BV(0) 

#define FUSE_BOOTSZ0     (unsigned char)~_BV(1) 

#define FUSE_BOOTSZ1     (unsigned char)~_BV(2) 

#define FUSE_EESAVE      (unsigned char)~_BV(3) 

#define FUSE_WDTON       (unsigned char)~_BV(4) 

#define FUSE_SPIEN       (unsigned char)~_BV(5) 

#define FUSE_JTAGEN      (unsigned char)~_BV(6) 

#define FUSE_OCDEN       (unsigned char)~_BV(7) 

#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) 

 

/* Extended Fuse Byte */ 

#define FUSE_BODLEVEL0   (unsigned char)~_BV(1) 

#define FUSE_BODLEVEL1   (unsigned char)~_BV(2) 

#define FUSE_BODLEVEL2   (unsigned char)~_BV(3) 

#define EFUSE_DEFAULT (0xFF) 

 

 

/* Lock Bits */ 

#define __LOCK_BITS_EXIST 

#define __BOOT_LOCK_BITS_0_EXIST 

#define __BOOT_LOCK_BITS_1_EXIST  

 

 

/* Signature */ 

#define SIGNATURE_0 0x1E 

#define SIGNATURE_1 0x94 

#define SIGNATURE_2 0x05 

 

 

#endif  /* _AVR_IOM169_H_ */

Forward mention:

in C, PORTB is type *(volatile uint8_t *)(0x20+0x08)
you'll want to understand what this means and will learn in this course

Useful Assembler Features

Though it may seem like extra work up-front work to learn to set symbolic names and use macros, they typically make writing assembly code much easier and easier to maintain, thus they are well-worth the upfront effort.

Preprocessor directive: DEFINE

Think of #define like a search-and-replace command that edits the source code before use
Use to make code readable and maintainable
Can replace use of .DEF tempreg, R16 in avr-assembler code

#define tempreg R16

Syntax:

#define Symbol Expression

Example:

#define tempreg R16  

#define ioreg R0 

...

 ldi tempreg,0xf0  ; Load 0xf0 into temp register  

 in ioreg,0x3f  ; Read SREG into ioreg register  

 eor tempreg,ioreg  ; Exclusive or tempreg and ioreg

MACRO

Multi-line macros can be defined using the following syntax

.macro pullupbpin somepinnum
  CBI DDRB , (\somepinnum); 
  SBI PORTB , (\somepinnum);
.endm

and invoked in the code like this

pullupbpin(4)

pullupbpin 4

Dcoumentation: https://sourceware.org/binutils/docs/as/Macro.html

Following taken and modified from http://support.atmel.no/knowledgebase/avrstudiohelp/mergedProjects/AVRASM/Html/directives.html

Example:

.MACRO SUBI16 arg0,arg1,arg2                  ; Start macro definition  

        subi arg1,lo8(arg0)         ; Subtract low byte  

        sbci arg2,hi8(arg0)        ; Subtract high byte  

.ENDM                           ; End macro definition

        SUBI16 0x1234,r16,r17   ; Sub.0x1234 from r17:r16

Note

hi8() and lo8() repace hi() and low() from standard avr asm

EQU,SET Directives

Allow assigning and reassigning of expressions to symbols

Syntax:

.EQU label, expression
.SET label, expression

Example: 
Example based on http://support.atmel.no/knowledgebase/avrstudiohelp/mergedProjects/AVRASM/Html/directives.html

.EQU io_offset ,0x23
.EQU porta, (io_offset + 2)

        clr r2        ; Clear register 2  
        out porta,r2  ; Write to Port A

; set FOO to point to an SRAM location 
.SET FOO,114 //Comment Allowed

lds r0, FOO ; load location into r0 

; increment (redefine) FOO. This would be illegal if using .EQU 
.SET FOO, FOO + 1

lds r1, FOO ; load next location into r1

equiv - Set once-only

The .equiv directive is like .equ and .set, except that the assembler will signal an error if symbol is already defined. Note a symbol which has been referenced but not actually defined is considered to be undefined.

.equiv symbol, expression

.eqv

The .eqv directive is like .equiv, but no attempt is made to evaluate the expression or any part of it immediately. Instead each time the resulting symbol is used in an expression, a snapshot of its current value is taken.

.eqv symbol, expression

#define to create a preprocessor function

Defining a preprocessor function-style macro "functions" using preprocessor directive #define

; bit mask macro identical to EXP2(),note use of shift operator  
#define BITMASK(X) (1<<X)  
#define BITMASK3(X1,X2,X3) (BITMASK(X1)+BITMASK(X2)+BITMASK(X3))

Stack and Functions

Using functions requires the stack. Using the stack requires that the stack pointer be initialized.

The following code shows how to initialize the stack pointer:

#define SomeReg R16 

    LDI SomeReg, HIGH(RAMEND) ; upper byte 
    OUT SPH,SomeReg           ;  
    LDI SomeReg, LOW(RAMEND)  ; lower byte 
    OUT SPL,SomeReg           ;

Then, code such as the following may be used:

PUSH SomeReg

POP SomeReg

RCALL SomeLabel

RET

pm_lo8 and pm_hi8 can be used to replace high() and low() from avr asm

https://sourceware.org/binutils/docs-2.21/as/AVR_002dModifiers.html#AVR_002dModifiers

Special-Purpose AVR Registers
- X,Y,Z are predefined
  X = r26:r27
  Y = r28:r29
  Z = r30:r31
- https://sourceware.org/binutils/docs-2.21/as/AVR_002dRegs.html#AVR_002dRegs

ldi	ZL,pm_lo8(myfunc)	; load z pointer
ldi	ZH,pm_hi8(myfunc)

icall			; indirect call to doSomething

myfunc:
   dec r16
   ret

For a tutorial on how to write subroutines, see

http://www.rjhcoding.com/avr-asm-functions.php
but note there is a subtle difference in syntax since we are using avr-as not avrasm syntax

Function/Subroutine Example

.equ	RAMEND,0x04ff
;Initialize the microcontroller stack pointer 
LDI    r16, lo8(RAMEND) 
OUT    SPL, r16
LDI    r16, hi8(RAMEND) 
OUT    SPH, r16

RCALL  delay

;Delay subroutine 
delay: LDI  R17, 0xFF 
loop:  DEC  R17 
       BRNE loop 
       RET

Derived from http://www.avr-tutorials.com/assembly/writing-assembly-subroutines-avr-microcontroller

ASM Example Setting IO with different access methods

(may step through code in simulator or debugger)

//.INCLUDE "m169Pdef.inc" 

.ORG 0x00000 

#define EXP2(x) (1<<(x))

//compute memory mapped io address 
.EQU io_offset , 0x20 
.EQU PORTA_MM , (io_offset + PORTA)  // PORTA is 0x02 
 
//set i/o bits using i/o register direct commands(cannot be used w/ ext. i/o regs) 
SBI PORTA, 6     //set bit I/O using bit number  
CBI PORTA, 6     //clear bit I/O 
SBI PORTA, 5     //set bit I/O 
 
//clear bit I/O using indirect access 
LDI ZL , lo8(PORTA_MM)  //load immediate to register 
LDI ZH , hi8(PORTA_MM) //low() and high() byte macros provided automatically 
LD R16, Z               //load indirect from memory to reguster R16 using memory address R31,R30 
CBR R16, EXP2(7)        //clear bitS in register requires mask instead of a bit number 
ST Z, R16               //store indirect to memory address R31,R30 from reguster R16  
 
//set bit I/O using indirect access 
LDI ZL , low(PORTA_MM) 
LDI ZH , high(PORTA_MM) 
LD R16, Z 
SBR R16, EXP2(7) 
ST Z, R16 
 
//clear bit I/O using direct (memory) access 
LDS R16 , PORTA_MM 
CBR R16, EXP2(6) 
STS PORTA_MM, R16 
 
//set bit in I/O using direct (memory) access 
LDS R16 , PORTA_MM 
SBR R16, EXP2(7) 
STS PORTA_MM, R16

Implementing Delays

Some options for implementing delays

Create a loop

ldi RTEMP, 255 ; 255 could also be a variable here 
the_delay: 
dec RTEMP 
brne the_delay

Use a few nop instructions

nop ; 1 clock 
nop ; 1 clock 
nop ; 1 clock

A combination for longer delays

ldi RTEMP, 255 ; 255 could also be a variable here 
the_delay: 
nop 
nop 
nop 
nop 
nop 
dec RTEMP 
brne the_delay

Create loops within loops

; outer loop 
ldi RTEMPB, 255 ; 255 could be a variable so the                                
               ; inner loop sets the delay step size 
outer_delay:  
; inner loop 
ldi RTEMPA, 122 ; 
inner_delay: 
nop 
nop 
nop 
nop 
nop 
dec RTEMPA 
brne inner_delay 
dec RTEMPB 
brne outer_delay

Using double-word operations for longer delays.

LDI 25, 0x01 //high 
LDI 24, 0xFF //low 
Loop: 
SUBIW R25:R24, 1 
BRNE Loop

Variablity and Cost/Utility of software delays

These types of software delays are dependent on the CPU clock frequency.
If the hardware clock frequency is changed, the actual delay time will change
- May opt to automatically change the number of iterations with clock frequency through macros, with counts derived from a provided clock frequency constant
- Not always trivial, espcially for small delays

nops and delay cycles correspond to unused processor capacitiy
there may be some productive work that can be done instead of using nops or using as many stall loops...maybe you can check button status while implementing a delay for blinking an LED. Replace the nops with productive instructions.

; outer loop 
ldi RTEMPB, 255 ; 255 could be a variable so the                                
               ; inner loop sets the delay step size 
outer_delay:  
; inner loop 
ldi RTEMPA, 122 ; 
inner_delay: 
nop        //    **DO OTHER WORK
nop        //    **DO OTHER WORK 
nop        //    **DO OTHER WORK
nop        //    **DO OTHER WORK
nop        //    **DO OTHER WORK 
dec RTEMPA 
brne inner_delay 
dec RTEMPB 
brne outer_delay

LDI 25, 0x01 //high **REDUCE
LDI 24, 0xFF //low **REDUCE
Loop: 
??????????   //    **DO OTHER WORK
??????????   //    **DO OTHER WORK
SUBIW R25:R24, 1 
BRNE Loop

Later, will learn to use on-chip digital timers to implement precise delays

Jumping based on single reister bits

Combining conditional Jumps with Unconditional Jumps
Conditional Jumps

SBIC- Skip if Bit in I/O Register Cleared
SBIS- Skip if Bit in I/O Register Set
SBRC- Skip if Bit in Register Cleared
SBRS- Skip if Bit in Register Set

Unconditional jumps

RJMP k :

Program execution continues at address PC + k + 1.
2 clock cycles.
The relative address k is from -2048 to 2047 (12 bits).

JMP k:

Program execution continues at address k
3 clock cycles
Can jump anywhere

So, how do we combine these?

#define JOYSTICK_INPORT PINB 
.equ UP_BUTTON_BIT , 5; 
.equ UP_BUTTON_MASK , (1<<UP_BUTTON_BIT);  
.equ UP_BUTTON_MASK_CMP , (0xFF - UP_BUTTON_MASK);  
#define RTEMP, r16

  ;skip if bit in register set followed by branch 
  ; branch occurs if button was pressed 
  sbis JOYSTICK_INPORT, UP_BUTTON_BIT 
  rjmp somewhere

In comparison,

   in RTEMP, JOYSTICK_INPORT 
   andi RTEMP, UP_BUTTON_MASK 
   brne somewhere

Example: waiting on a bit to change to a 1

back_here:  
  SBIS PINB, 0 
  rjmp back_here 
  <some other code>

How to check on or wait for one of multiple bits?
Covered in previous lecture.

Use defines and equ were possible to make code readable and maintainable

.equ BUTTON_CHECK_MASK  , (UP_BUTTON_MASK  +  DOWN_BUTTON_MASK)

Tables

Larger constants, e.g. arrays and strings, can be stored in the program memory instead of being encoded in immediate operands

MyByteTable:
.byte 0x12,0x34,0x56,0x78
.byte 0xDE,0xED,0xBE,0xEF  

...

LDI ZH,hi8(MyByteTable) ; Put address of table in pointer Z
LDI ZL,lo8(MyByteTable) ; 

ADIW ZL,6 ; access 6th element 
LPM ; red byte from program memory into R0

...

Switch/Case and Jump Tables

Useful GAS (GNU AS) modifiers:

lo8(),hi8(): get low or high byte of a word
pm_hi8(),pm_lo8() : denotes intention to access a byte program memory (flash) using a relocatable-address expression
pm() allows for storage of a relocatable program memory adress as the word-address instead of a byte address
https://sourceware.org/binutils/docs/as/AVR_002dModifiers.html

Implementation of Case

First will try to directly compute jumps, assuming a regular spacing of case starting points (i.e. each has the same number of instructions)
Can be useful if switch-case code is only function calls

Misc. code to setup jump experiment, taking place of real actionable code:

#define instructions_per_case (2)
#define select (2)

ldi r16,lo8(select*instructions_per_case)
ldi r17,hi8(select*instructions_per_case)

Implemenation of CASE assuming that the offset is represented in r17:r16

;Example Implementation of Case
LDI ZH,pm_hi8(CaseTable) ; First address into pointer register Z
LDI ZL,pm_lo8(CaseTable) ; 
                         ; Add instruction offset (word/instruction address)
add ZL,r16               ; Add low byte
adc ZH,r17               ; Add with carry high byte

ijmp                     ; jmp using location stored in Z

CaseTable:
CASE0:
    LDI R25,100;
    rjmp ENDCASE
CASE1:
    LDI R25,110;
    rjmp ENDCASE
CASE2:
    LDI R25,120;
    rjmp ENDCASE
ENDCASE:

    mov r0,r0 ;dummmy instruction easy to find in program memory

Inline Jump Vectors

Try to implement cases with varying code sizes.
Direct compution of each jump offset is problematic
Use two jumps
- First vector of jumps is regularly spaced in program memory

#define select (1)

ldi r16,lo8(select)
ldi r17,hi8(select)

;Inline Jump Table
LDI ZH,pm_hi8(InlineJumpTable) ; First address into pointer register Z
LDI ZL,pm_lo8(InlineJumpTable) ;
add ZL,r16 ; Add low byte      
adc ZH,r17 ; Add with carry high byte
ijmp
InlineJumpTable:
ICASE0: rjmp HandleCASE0
ICASE1: rjmp HandleCASE1
ICASE2: rjmp HandleCASE2

HandleCASE0:
    LDI R25,120;    
    LDI R25,110;    
    LDI R25,100;    
    rjmp ENDCASE
HandleCASE1: 
    LDI R25,120;    
    LDI R25,110;    
    rjmp ENDCASE
HandleCASE2: 
    LDI R25,100;    
    rjmp ENDCASE
ENDCASE:

    mov r0,r0 ;dummmy

Jump Table

Use a table of stored locations of case code
On AVR, first must use load program memory instruction (lpm)
- lpm that assumes a byte address is stored in Z
- Store jump locations in data table using pm()

#define bytes_per_instruction_address (2)
#define select (2)

ldi r16,lo8(select*bytes_per_instruction_address)
ldi r17,hi8(select*bytes_per_instruction_address)

LDI ZH,hi8(MyJumpTable) ; Prepare pointer Z to access bytes of program/flash memory
LDI ZL,lo8(MyJumpTable) ; 
                        ; Offset
add ZL,r16              ; Add low byte
adc ZH,r17              ; Add with carry high byte
                        ; Load location into Z, using part of Y as a temporary variable
lpm YL,Z+               ;   (could have used any other 8-bit register, nothing special about using YL)
lpm ZH,Z
mov ZL,YL
ijmp
MyJumpTable:
.word pm(JTCASE0)      ; pm() modifier, otherwise unwanted byte address (word address x2) is stored here
.word pm(JTCASE1) 
.word pm(JTCASE2) 
JTCASE0:
    LDI R25,120;    
    LDI R25,110;    
    LDI R25,100;    
    rjmp JTENDCASE
JTCASE1: 
    LDI R25,120;    
    LDI R25,110;    
    rjmp JTENDCASE
JTCASE2: 
    LDI R25,100;    
    rjmp JTENDCASE
JTENDCASE:    

    mov r0,r0 ;dummmy

C to Assembly Examples

Start a debug session, right click on the code you're debugging and right click and select Goto Dissasembly.
--Pasted from http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=58624

C to Assembly Example

#include <avr/io.h>  

int main(void){  
  unsigned char a;        
  unsigned char b;       
  a = 0b00000000;       
  b = 0b00000100;  
  DDRB = 255;  
  for(;;)  
   {  
     PORTB = a;    
    PORTB = b;    
  }      
  b = a; //no reason  
return(0);  
}

0000005c <__ctors_end>:  
  5c:          11 24        eor  r1, r1   //exclusive or R1 with itself  --r1=0;  
  5e:          1f be        out  0x3f, r1    ; 63  //0x3f is SREG ---clearing all status bits  
  60:          cf ef          ldi  r28, 0xFF ; 255   --0xFF  
  62:          d4 e0        ldi  r29, 0x04 ; 4    --0xF  
  64:          de bf        out  0x3e, r29 ; 62   -- SPH  
  66:          cd bf         out  0x3d, r28 ; 61    --SPL  
   --- last 2 instructions set the Stack Pointer to the last address of memory (0xFFF)  
  68:          0e 94 3a 00   call  0x74         ; 0x74 <main>   --- call subroutine (our main)   
  -- last instuction will cause PC to be pushed on stack, (2 pushes)  - SP wil be 0xFFD  
  6c:          0c 94 52 00   jmp           0xa4         ; 0xa4 <_exit>

int main(void)  
{  
  74:          df 93        push         r29   ---> SP = 0xFFC  
  76:          cf 93         push         r28    --->SP = 0xFFB  
  --last 2 insts will push Y register in top of stack  --why?     
  --when we go to a routine, we should push general registers that we wanna use in  our routine, since   
  --they may be used out side of our routine and we might lose the data.  
  78:          00 d0        rcall          .+0            ; 0x7a <main+0x6>   
  -- relative call to our routine (this opens up 2 byes space on top of stack) why 2 bytes?  
  --these will be our variables  (a and b)   a is at 0xFFB, and b is at oxFFA  
  --remember SP will be decrease 2 times here---> SP = 0xFF9  
  7a:          cd b7        in  r28, 0x3d ; 61    
  7c:          de b7        in  r29, 0x3e ; 62  
  ---last 2 instructions will load Y register with SP    ( Y will be 0xFF9 )  
  unsigned char a;  
  unsigned char b;

a = 0b00000000;  
  7e:          1a 82        std  Y+2, r1     ; 0x02 --- (Y+2) <- R1; R1 is zero.  Y+2 is  
0xFFB (this is setting a =0;  
  b = 0b00000100;  
  80:          84 e0        ldi  r24, 0x04 ; 4  -- load "4" into r24;  
  82:          89 83        std  Y+1, r24   ; 0x01  --(Y+1)<- R24; --- set Y+1  
(means "b") to "4"  
  
  DDRB = 255;  
  84:          84 e2        ldi  r24, 0x24 ; 36    --- DDRB  is at address 0x24  
  86:          90 e0        ldi  r25, 0x00 ; 0       
  88:          2f ef         ldi  r18, 0xFF ; 255    -- R18 <- 0xFF  
  8a:          fc 01         movw      r30, r24  --- R31:R30 <- R25:R24   (Z <- 0x24)  
  8c:          20 83        st  Z, r18  ---  (z) <- R18   (write oxFF into DDRB)

for(;;)  
    {  
    PORTB = a;         // set PB2 to 1  
  8e:          85 e2        ldi  r24, 0x25 ; 37   -- PORTB is located at address 0x25  
  90:          90 e0        ldi  r25, 0x00 ; 0  
  92:          2a 81        ldd  r18, Y+2   ; 0x02   (load variable a into R18)  
  94:          fc 01         movw      r30, r24        
  96:          20 83        st  Z, r18    -- (z) <- R18   (R18 contains varibale a)

C to assembly with a function call

/* 
 * GccApplication1.c 
 * 
 * Created: 9/10/2012 11:26:40 AM 
 *  Author: rrobucci 
 */  
 
 
#include <avr/io.h> 
 
 
uint8_t myFunc(uint8_t a,uint8_t b) { 
register c; 
c = a+b; 
return c; 
} 
 
 
int main(void) 
{ 
 
uint8_t A,B,C; 
A=1; 
B=2; 
C= myFunc(A,B); 
    C = C+1;  
    while(1) 
    { 
        //TODO:: Please write your application code  
    } 
}

Disassembly:

--- No source file ------------------------------------------------------------- 
00000000  JMP 0x0000002E Jump  
00000002  JMP 0x0000004B Jump  
00000004  JMP 0x0000004B Jump  
00000006  JMP 0x0000004B Jump  
00000008  JMP 0x0000004B Jump  
0000000A  JMP 0x0000004B Jump  
0000000C  JMP 0x0000004B Jump  
0000000E  JMP 0x0000004B Jump  
00000010  JMP 0x0000004B Jump  
00000012  JMP 0x0000004B Jump  
00000014  JMP 0x0000004B Jump  
00000016  JMP 0x0000004B Jump  
00000018  JMP 0x0000004B Jump  
0000001A  JMP 0x0000004B Jump  
0000001C  JMP 0x0000004B Jump  
0000001E  JMP 0x0000004B Jump  
00000020  JMP 0x0000004B Jump  
00000022  JMP 0x0000004B Jump  
00000024  JMP 0x0000004B Jump  
00000026  JMP 0x0000004B Jump  
00000028  JMP 0x0000004B Jump  
0000002A  JMP 0x0000004B Jump  
0000002C  JMP 0x0000004B Jump  
0000002E  CLR R1 Clear Register --initialize stack pointer  
0000002F  OUT 0x3F,R1 Out to I/O location  
00000030  SER R28 Set Register  
00000031  LDI R29,0x04 Load immediate  
00000032  OUT 0x3E,R29 Out to I/O location  
00000033  OUT 0x3D,R28 Out to I/O location  
--- C:\home\tools\hudson\workspace\avr8-gnu-toolchain\src\gcc\gcc\config\avr\libgcc.S  
 
00000034  LDI R17,0x01 Load immediate  
--- C:\home\tools\hudson\workspace\avr8-gnu-toolchain\src\gcc\gcc\config\avr\libgcc.S  
 
00000035  LDI R26,0x00 Load immediate  
 
00000036  LDI R27,0x01 Load immediate  
 
00000037  LDI R30,0xF8 Load immediate  
 
00000038  LDI R31,0x00 Load immediate  
 
00000039  RJMP PC+0x0003 Relative jump  
 
0000003A  LPM R0,Z+ Load program memory and postincrement  
 
0000003B  ST X+,R0 Store indirect and postincrement  
 
0000003C  CPI R26,0x00 Compare with immediate  
 
0000003D  CPC R27,R17 Compare with carry  
 
0000003E  BRNE PC-0x04 Branch if not equal  
 
0000003F  LDI R17,0x01 Load immediate  
 
00000040  LDI R26,0x00 Load immediate  
 
00000041  LDI R27,0x01 Load immediate  
 
00000042  RJMP PC+0x0002 Relative jump  
 
00000043  ST X+,R1 Store indirect and postincrement  
 
00000044  CPI R26,0x00 Compare with immediate  
 
00000045  CPC R27,R17 Compare with carry  
 
00000046  BRNE PC-0x03 Branch if not equal  
--- No source file ------------------------------------------------------------- 
00000047  CALL 0x00000067 Call subroutine  
00000049  JMP 0x0000007A Jump  
0000004B  JMP 0x00000000 Jump  
--- C:\Users\rrobucci\Documents\Atmel Studio\GccApplication1\GccApplication1\No Optimization/.././GccApplication1.c  
uint8_t myFunc(uint8_t a,uint8_t b) { 
0000004D  PUSH R16 Push register on stack --push registers that will be dirtied 
0000004E  PUSH R17 Push register on stack  
0000004F  PUSH R28 Push register on stack  
00000050  PUSH R29 Push register on stack  
00000051  RCALL PC+0x0001 Relative call subroutine -- makes room for 2 bytes for local variable a and b 
00000052  IN R28,0x3D In from I/O location  
00000053  IN R29,0x3E In from I/O location  
00000054  STD Y+1,R24 Store indirect with displacement  
00000055  STD Y+2,R22 Store indirect with displacement  
--- C:\Users\rrobucci\Documents\Atmel Studio\GccApplication1\GccApplication1\No Optimization/.././GccApplication1.c  
c = a+b; 
00000056  LDD R24,Y+1 Load indirect with displacement  
00000057  MOV R18,R24 Copy register  
00000058  LDI R19,0x00 Load immediate  
00000059  LDD R24,Y+2 Load indirect with displacement  
0000005A  MOV R24,R24 Copy register  
0000005B  LDI R25,0x00 Load immediate  
0000005C  MOVW R16,R18 Copy register pair  
0000005D  ADD R16,R24 Add without carry  
0000005E  ADC R17,R25 Add with carry  
return c; 
0000005F  MOV R24,R16 Copy register -- R24 used for return parameter 
} 
00000060  POP R0 Pop register from stack --throw away local variables on stack, a and b 
00000061  POP R0 Pop register from stack  
00000062  POP R29 Pop register from stack --restore registers 
00000063  POP R28 Pop register from stack  
00000064  POP R17 Pop register from stack  
00000065  POP R16 Pop register from stack  
00000066  RET Subroutine return  
{--main 
00000067  PUSH R28 Push register on stack --save registers that will be dirtied 
00000068  PUSH R29 Push register on stack  
00000069  RCALL PC+0x0001 Relative call subroutine --moves stack pointer by 2 bytes to make room for local variables (saving of PC is not significant) 
0000006A  PUSH R0 Push register on stack --  moves stack pointer by 1 byte to make room for local variables 
0000006B  IN R28,0x3D In from I/O location --save stack pointer to R29:R28 aka Y for easy access 
0000006C  IN R29,0x3E In from I/O location  
A=1;--A lives at Y+1 
0000006D  LDI R24,0x01 Load immediate  
0000006E  STD Y+1,R24 Store indirect with displacement  
B=2;--B lives at Y+2 
0000006F  LDI R24,0x02 Load immediate  
00000070  STD Y+2,R24 Store indirect with displacement  
C= myFunc(A,B); --use R24 and R22 as for parameter passing and R24 for return later 
00000071  LDD R24,Y+1 Load indirect with displacement  
00000072  LDD R22,Y+2 Load indirect with displacement  
00000073  CALL 0x0000004D Call subroutine --pushes PC to stack 
--- C:\Users\rrobucci\Documents\Atmel Studio\GccApplication1\GccApplication1\No Optimization/.././GccApplication1.c  
00000075  STD Y+3,R24 Store indirect with displacement --return value in R24 stored where C lives Y+3 
    C = C+1; --now use R24 as a working register, C lives in Y+3 
00000076  LDD R24,Y+3 Load indirect with displacement  
00000077  SUBI R24,0xFF Subtract immediate --same as adding 1 or inc R24 
00000078  STD Y+3,R24 Store indirect with displacement  --put result where C lives 
    } 
00000079  RJMP PC-0x0000 Relative jump -- infinite while loop 
--- C:\home\tools\hudson\workspace\avr8-gnu-toolchain\src\gcc\gcc\config\avr\libgcc.S  
 
0000007A  CLI Global Interrupt Disable  
 
0000007B  RJMP PC-0x0000 Relative jump  
--- No source file ------------------------------------------------------------- 
0000007C  NOP Undefined  
0000007D  NOP Undefined  
0000007E  NOP Undefined

Lecture 06 – More AVR Assembly

Table of Contents

Needs Update

Assembler

Device-Specific Header/Include File

m169pdef.inc listing

Iom169.h listing

Useful Assembler Features

Preprocessor directive: DEFINE

MACRO

EQU,SET Directives

equiv - Set once-only

.eqv

#define to create a preprocessor function

Stack and Functions

Implementing Delays

Variablity and Cost/Utility of software delays

Jumping based on single reister bits

Tables

Switch/Case and Jump Tables

Implementation of Case

Inline Jump Vectors

Jump Table

C to Assembly Examples