Lecture – Data Converters

Ryan Robucci

Lecture – Data Converters

References

Representing Real Numbers Limited # of Bits

Many physically-based values are best represented with real-numbers as opposed to a discrete number of values. However, in computers we are practically limited in the number of distinct values we can represent.
So, how can we represent real numbers?
- We create a mapping of codes to physical values such as the
  following.

Want to represent 0 - 10 V with three bit.

Can only pick 8 real-valued points called the quantization levels.
Many such choices exist

Digital Code to Real Value Mapping

Quantization: "rounding" of real number to one of a limited set real-numbered quantization levels
Quantization error ( $Q_e$ ): is the difference between a desired real number and its quantized value
Coding: mapping of set of real numbers to a digital code
Most common : 8 levels, equally spaced with first level at $0\ [\rm V]$ and highest at $10\ [\rm V] \times \frac{2^N-1}{2^N}$
- $\rm code \rightarrow value$ $code \to value$ conversion:
  - $\frac{\rm code}{2^N} V_{\rm ref} \rightarrow \rm Value$
- $\rm value \rightarrow code$ $value \to code$ conversion:
  - $\rm round\left(\frac{\rm value}{V_{ref}}\times 2^N\right)$
    bounded to range $0$ to $2^N-1$
- The maximum value that can be represented by the code is $\frac{2^N-1}{2^N}\times V_{\rm ref}$

Comparison to binary number representation

Common binary codes use POWERS OF TWO for bit weights

$\displaystyle \sum_{i=0}^{n-1}(\underbrace{2^i}_{\mathrlap{\text each\ weight\ is\ twice\ the\ previous}} x_i )$

The A/D coding just described uses real-valued weightings instead, increasing by powers of two:

${\rm voltage} = \displaystyle \sum_{i=0}^{n-1} \underbrace{\frac{V{\rm ref \times 2^i}}{2^N}}_{\mathrlap{\text voltage\ weight}} x_i$

The step size between quantization levels corresponds to the real-value weighting of the LSB:
resolution or step size: $1 \leftrightarrow \frac{V{\rm ref}}{2^N}$

Lets represent the voltage range [0 V, 10 V) with a three bit code.

2	1	0	Value
0	0	0	0 Vref/8
0	0	1	1 Vref/8
0	1	0	2 Vref/8
0	1	1	3 Vref/8
1	0	0	4 Vref/8
1	0	1	5 Vref/8
1	1	0	6 Vref/8
1	1	1	7 Vref/8

Time for Conversion

A/D or D/C converters require a finite amount of time per conversion, and therefor must must also be characterized in time

ADC Conversation Time: latency from sample update to output update
ADC Sampling Rate: max rate of sampling
DAC Settling Time: time to settle to a new value within some error, usually .0.5 Vlsb

A Digital to Analog Converters (DAC)

A common circuit provides binary-weighted contributions:

Middle node held to 0V
resisters are valued by powers of two
each resister conducts a power of two times any other
Summed current flows through final R to generate an output voltage.

Example:
1 (on)
0 (off)
1 (on)
$\rightarrow \left(1/2 + 1/8 \right) \times V_{\rm ref}$

Digital inputs set output voltages
Requires many different valued precise, accurate resistances
Analog Design note: must account for resistance of switches

Resolution

Resolution: in scientific context is the minimal difference between two values that can be resolved.
- change represente by $\pm 1$ in digital code, $V_{lsb}$
- For converters it often is used instead as an in informal shorthand for "number of bits of resolution"..."What is the resolution?": 12 bits
number of bits of resolution : the number of quantization levels or the number of bits $N=\log_2 (\# levels)$
Effective number of bits (ENOB): effective accuracy characterized with a full-scale sinusoidal wave input
- Not only the number of bits, but all accounts for offset and gain errors as well as timing jitter

Enrichment: Offset and Gain Error: typical to quantify in terms of bits

Offset and Gain Error
- typical to quantify total error in terms of bits
- number of bits of error = $\rm V_{error} / V_{full\, scale} * 2^n$
- offset error: is measured at one point, typically near zero but may choose others
- gain error: measured by horizontally shifting transfer curve to origin (can also use midpoint or best fit shift) and finding maximum error
DNL: differential non-linearity is the max deviation of a step size from the ideal
- defined by most erroneous step
INL: maximum deviation of any quantization code threshold form the ideal
- defined by sum of erroneous steps, accumulated step error, though +/- step errors may cancel

Sample Time Jitter

Jitter in sampling time causes error proportional to the jitter time and the rate of change of a signal
sample time uncertainty can be affected by input clock jitter or other uncertainty in trigger
- In HW5, we use the hardware to directly trigger the DAC, and use software to unload the value
Largest impact when signal is changing
- for a sine wave the worst case is mid-rail, at the instant of the highest derivative

Sample Error $\Delta v= \Delta t \times \frac{d\,v(t)}{dt}$
Worst-Case Error $\Delta v= \Delta t \times \underset{t}{\max} \left(\frac{d\,v(t)}{dt}\right)$

Enrichment: Jitter and Sinewaves

Analysis for allowed jitter under sine-wave input condition:

For a size wave, max rate of change is proportional to the wave amplitude and frequency
$\frac{dV}{dt} \propto A,f$

$\underset t \max \frac{dV(t)}{dt}$ for $V(t)=A \sin \left(2 \pi f t\right)=A 2\pi f$
Let the full-scale voltage of the ADC be $V_{\rm FS}$
Max A is $V_{\rm FS}/2$
Therefore worst case is $\frac{dV(t)}{dt}=V_{FS} \pi f$
Max error in this case is
$\Delta V=V_{\rm FS} \pi f\Delta t$
To ensure $\Delta V \lt V_{\rm LSB}=\frac{V_{\rm FS}}{2^N}$ ,
$\Delta t \frac{1}{2^N \pi f}$
which is the allowed time jitter for a sample of a sine-wave input of frequency f to ensure that jitter-induced error is less than one $V_{\rm LSB}$

Enrichment: Dynamic Range

Dynamic Range:

ratio of the rms of the max sine wave to the rms of noise and distortion errors
typically would be dependant on freq. of sine wave and the amplitude
may define effective number of bits $\rm ENOB = \log_2 \left( \frac{\text{full-scale sine RMS}}{\text{noise RMS+dist. RMS}} \right)$ $ENOB = lo g_{2} (\frac{full-scale sine RMS}{noise RMS+dist. RMS})$
- noise RMS includes quantization and other system noise

Quantization Error

through the process of quantization, a signal is estimated by mapping it to a finite set of values
In our content the set represents analog values called teh quantization levels and the sequence chosen represents the estimation or approximation of the signal
- i.e. represent an analog signal with a time series of digital codes
The difference between the estimate and the true value is called the quantization error
In the follow graphic, assume a perfect, ideal D/A converter to think about the error of an A/D:
For a known characteristic signal, error can be estimated:
- Example: ramp signal
- Also typical to use a sinusoid for performance characterization

Other DACs

R-2-R Ladder DAC

Only 2 precise resistor values are required, exact value of resistance doesn't matter as much matching among them
The error of each resistor spread across codes more than previous
Monolithic implementations available (constrains errors to guarantee that increasing code always corresponds to a higher value...important for some feedback and control applications)

Current-Output DACs

Output is current instead of voltage
Common for high-speed converters
Voltage can be set using a resistor or by a user-selected external high-speed active current-to-voltage converter

Direct Current DAC Architecture:

PWM-based DAC

A cheap DAC can be built using digital driver and a low-pass filter. The duty cycle of the digital signal sets the analog output level.

ADC

An analog-to-digital conversion (abbreviated ADC, A/D or A to D) is a process that converts a continuous quantity (continuous in time and possible values ) to a discrete-time, discrete value (digital) representation

ADC is:
- Mapping to discrete values
- Updating/defining value at discrete times
  - (actually, discrete-value continuous-time converters are possible but not conventional)

Analog Waveform to Digital Waveform

Top-Left Images Courtesy Spinningspark at Wikipedia provided by Attribution-ShareAlike 3.0 Unported https://creativecommons.org/licenses/by-sa/3.0/, all images from Wikipedia

ADCs may use
- Single or parallel stages
- Single conversion step or successive approximation steps
- One or multiple clock cycles
The various architectures trade off the performance metrics
discussed, as well as cost, power, size, etc...

Common ADC Architectures

Flash
Pipelined
Successive-Approximation
Sigma-Delta

order here is generally trending towards slower and more accurate

Flash Converter: uses parallel stages for speed, precision/accuracy is
sacrificed by needing many so many parts matched
Pipelined Converter: uses multiple stages to resolve signal, good throughput but larger latency
Successive Approximation (and Algorithmic Converters): uses multiple iterations to resolve signal, slow
Sigma-Delta: performs fast conversion on signal changes but effectively slow sensing/ detections of total signal/large changes

Performance Metrics

Sample rate/ throughput: number of measurements of amplitude per second. Higher sampling rates are better but increase data-rates, power, cost, etc...
Required Sampling Rate: How fast is fast enough? The commonly-cited value is 2-times the frequency of the highest frequency component into the ADC, (this allows perfect reconstruction of the continuous waveform)Often an analog low-pass filter is used before the ADC to limit the required sampling frequency.
Oversampling: Sometimes a technique call oversampling is used: it involves sample faster and digitally averaging results to remove some noise. For AVR, see application note http://www.atmel.com/images/doc8003.pdf
Latency: time between sampling a voltage and getting the corresponding value
Bit depth :determines number of discrete values that can be represented, sets bound on combination of precision and range of each measurement of amplitude.
Precision vs Accuracy:
- If the offset of the measured value from the true value maters, then you are considering accuracy.
- If you care how small of a voltage step you can resolve, then you are considering precision.
- Often these ideas are combined informally under the umbrella term "accuracy"
- (Look up INL/DNL: integral and differential error to find formal metrics used for converters.)
Monolithic:
- ADC: means that digital codes increase, or at worst doesn't decrease, when analog voltage increases
- DAC: means that analog voltages increase,or at worst doesn't decrease, then the digital code increases
- Non-monotonic is very bad for control systems, since a change will have the opposite impact expected

ADC Differential and Pseudo-differential Input

Differential input is useful when the potential to be measured is not referenced to
ground.
It is also useful for rejecting noise on ground or differences between grounds

Pseudo-differential is like differential but Vin- pin must be close in terms of voltage to ground. (~.7) and is used only for noise rejection.

ADC Sample-and-Hold

A Sample and Hold (S/H) is required to hold an analog signal while a (initial) conversion can complete
The most basic S/H is a switch and a capacitor. Shown below is an ideal sample, as well as two non-ideal effects to be discussed.

ADC Sample and Hold - Driving Sampling Capacitor and Track and Hold Input Buffer

For fast operation, a driver must be able to set the capacitor quickly and accurately. For fast settling a small RC is required, i.e. a low output resistance is required by the driver. For this purpose, the ADC datasheet may specify a maximum output impedance for the driver along with a minimum current drive ability.

Some ADCs include a internal "Track and Hold" buffer to drive the sample capacitance

Does our AVR Include a Track and Hold buffer?

Switch Leakage and Droop result in finite hold time

A Sample-and-Hold is required to Hold the signal while a conversion can start/complete
The switch is implemented with FET that unfortunately leaks current and causes droop during hold.
So, hold times can not be indefinite and thus ADC's often require a minimum clock rate to
ensure processing happens quickly enough.

Clock and Charge Feedthrough

Turning off the switches introduces unwanted charge into the output node.
This can be observed by a "jump" in the signal at sample time.

Common Analog to Digital (ADC) Architectures

Flash Converter

Digital Ramp ADC

ADC built from a DAC
An analog approximation "guess" is made by increasing a digital code to a DAC.
Once the analog approximation crosses the input, waveform is reached, the digital code is saved

Tracking ADC

An analog approximation "guess" is made by stepping the previous digital code up or down each cycle.
- Can transmit only the step information
This is fast and works well if the analog input waveform doesn't move too quickly.

Integrating Reference Ramp ADC

An analog approximation is made in the analog domain by integrating a constant current onto a capacitor.
A digital timer determines the analog value by the time needed for the approximation to reach the analog input.

Dual-Slope ADC

Measures time to discharge a capacitor based on input signal
Very precise, but slow
Value based on one R and one C (Assuming amplifier gain is large), but can be calibrated

Pipelined and Algorithmic ADC

"multistage" converters that use multiple stages to complete a conversion
- first stages generally providing the most-significant bits and latter stages providing the least-significant bits
- have inherent latency

Pipelined-ADC

Replaces N-bit converter with m stages of $\frac{N}{m}$ $\frac{N}{m}$ -bit converters
- though typically extra bits are used for digital error correction
Each subsequent stage converter works on a smaller residual (smaller range) with better analog precision

Algorithmic ADC

multiplies residual error rather than rather than converting successively smaller signals
Each subsequent stage converter works with and analog range analog precision

Pipelined:

Successive-Approximation ADC

(Binary Search ADC)

• slower than flash, takes several iterations
• accuracy determined by DAC & Comparator

Example: Low Power Successive-Approximation Charge Charge-Based ADC

Delta Converters

Key Observation: common analog signals have a bounded change in a given time
So, focus on converting small changes and do it so fast that only small changes need to be digitized using low-resolution components
Maintain an internal error cumulative error estimate, and use only small +/- deltas to reduce the error

Sigma Delta ADC

A feedback loop maintains an estimate and use only deltas to adjust the estimate
By sampling quickly, digital signal processing can be employed to reduce noise

Sigma Delta DAC

basically swap digital and analog parts

http://www.analog.com/static/imported-files/application_notes/292524291525717245054923680458171AN283.pdf

ADC of Atmega169P

10-bit Resolution

0 - VCC ADC Input Voltage Range
ADC clock can be 50KHz to 1MHz
Full resolution (10 bits) frequency range 50KHz-200KHz
Up to 15 ksps at to get Maximum Resolution (200 kHz ADC clock)
NOTE the 200 kHz ADC clock and compared to the 15 ksps spec.
http://www.atmel.com/Images/doc8018.pdf
Conversion Timing: Each conversion takes 13 clocks,
- So, ADC clock = 200KHz----> 200KHZ/13HZ ~15K sample (15ksps)

More Info: Characterization and Calibration of the ADC on an
AVR http://www.atmel.com/dyn/resources/prod_documents/doc2559.pdf

Sampling Rate

Nyquist Rate: Required Sampling Frequency

Required sampling rate: $f_{\rm nyquist\ rate}> 2 \times f_{\rm signal}$
Time Sampling Demo: https://editor.p5js.org/robucci/full/gAxRREU12 (!WARNING FLASHING!)

Undersampling and Aliasing

Term "aliasing" comes from a frequency-domain view of a signal
- Cannot distinguish between some some frequencies
- Can uniquely distinguish sinusoidal signals with frequencies below 1/2 the sampling rate

Here, two sinusoidal signals are sampled.
With only the samples provided, a system could not know which sinusoid produced the samples.

A higher sampling rate is required to distinguish these signals

Here, samples of sinusoid are no different than that from a DC signal:

In this next example, spatial aliasing is shown

Full-Scale:

Using every 8th pixel: aliasing creates appearance of wide structures on the right

Using every 16th pixel: lower fidelity of structure

Oversampling

Oversampling can reduce noise. Many samples are taken to represent the signal, and a technique such as averaging can reduce noise.
- https://ww1.microchip.com/downloads/en/Appnotes/doc8003.pdf

In a Signal Processing Course, you can learn to model this in the frequency domain:

Sampling sample faster than required causes white noise to be representend over a larger frequncy range, with allows a digital low-pass filter to remove noise well beyond the signal frequency.