Course Title : Programmable Logic Devices
Course Number : CMPE 316
Credits: 3.00
Description: This course covers the concepts, structure and programming characteristics of programmable logic devices such as PLDs and FPGAs. Hardware Description Languages (HDLs) are used to create designs that are tested on FPGA devices.
Prequisite : You must complete CMPE 310 with a grade of C or better.
Instructor
Dr. Ryan Robucci

Assistant Professor
Email: robucci@umbc.edu
Department of Computer Science and Electrical Engineering
University of Maryland Baltimore County
1000 Hilltop Circle
Baltimore, MD, 21250
Office: ITE 319 Office Hours: TBD
Phone: 410-455-3549

Meeting Time MoWe 1:00-2:15 ITE 241

Teaching Assistants and Graders :

Syllabus : link


(used blackboard for discussion this semester)


Calendar

Date Event Description/Reading Assignments and Due Dates
Jan 28 First Lecture Course Introduction, Intro to FPGAs Reading for Next Class Copyright Elsevier, for class use only
Jan 29 Lecture 01 FPGA Technology I -
Feb 03 Lecture 02 FPGA Technology II (link protected) -
Feb 05 Lecture 03 Verilog Introduction I -
Feb 6 Assignment 1 - HW1 Tool Installation https://eclipse.umbc.edu/robucci/cmpe316/hw1/vivado/vivado.html Due: Feb 12th up to three days late no penalty
Feb 10 Lecture 04 Verilog Introduction II -
Feb 12 Lecture 05 Verilog Introduction III -
Feb 12 Assignment 1 Due -
Feb 12 Assignment 2 - HW2 Due Feb 19th
Feb 17 Lecture 06 Events Timing Testbeches -
Feb 19 Quiz 1 - -
Feb 19 Assignment 2 Due - -
Feb 19 Assignment 3 - HW3 Due Feb 26th
Feb 24 Lecture 07 Debugging and Monitoring -
Feb 24 Lecture 08 Full and Parallel Case -
Feb 26 Lecture 09 Suggested Coding and Design Practices -
Feb 26 Assignment 3 Due - -
March 27 Assignment 4 Part A - HW4 Part A Due Mar 5
March 04 Last Day to Widthdraw https://registrar.umbc.edu/wp-content/uploads/sites/31/2024/08/Spring-25-UGRD-Calendar.pdf -
March 05 Assignment 4 Part A Due -
Mar 27 Assignment 4 Part B - HW4 Part B Due Mar 13
Mar 10 Quiz 2 - -
March 10 Lecture 10 Operators_Operands_Variables_Literals -
Mar 12 Quiz 3 - -
Mar 13 Assignment 4 Part B Due -
March 15 Spring Break Ends on March 23th -
Mar 26 Lecture 11 Synth and Loops -
March 31 Exam I -
Apr 2 Lecture 12 FSM I -
May 13 Last Day of Classes -
Apr 14 Lecture 13 FSM II -
Apr 14 Quiz 4 - -
Apr 16 Assignment 5 - HW5 Part A: Due April 28th, Part B: Due May 2
April 23 Lecture 14 Parameterized Modules and Simulation, Timing, Testbenches and More Advanced Verilog -
Apr 28 Assignment 5 PART A Due - HW5 Part A Due
April 28 Lecture 15 Physical Design Flow and Timing Analysis https://eclipse.umbc.edu/robucci/applets/timing_violations/ -
Apr 30 Midterm II -
May 2 Assignment 5 PART B Due !!!UPDATED DATE ANNOUNCED IN CLASS!!! HW5 Part B Due
May 5 Assignment 6 Assigned - HW6
May 7 Quiz 5 Physical Design Flow and Timing Analysis
May 12 Lecture 16 FPGA Technology III -
May 13 Assignment 6 Due - HW6
May 21 Final Exam (Wed) 1PM-3PM https://registrar.umbc.edu/wp-content/uploads/sites/31/2025/01/Spring-2025-Regular-Exam-Schedule.pdf -
Previous
Date Event Description/Reading Assignments and Due Dates
Jan 29 First Lecture Course Introduction, Intro to FPGAs Reading for Next Class Copyright Elsevier, for class use only
Jan 31 Lecture 01 FPGA Technology I -
Feb 05 Lecture 02 FPGA Technology II (link protected) -
Feb 07 Lecture 03 Verilog Introduction I -
Feb 7 Assignment 1 - HW1 Tool Installation https://eclipse.umbc.edu/robucci/cmpe316/hw1/vivado/vivado.html Due: Feb 14th
Feb 12 Lecture 04 Verilog Introduction II -
Feb 14 Lecture 05 Verilog Introduction III -
Feb 19 Lecture 06 Events Timing Testbeches -
Feb 19 Assignment 2 - HW2 Due: Feb 28th
Feb 21 Lecture 07 Debugging and Monitoring -
Feb 26 Lecture 08 Full and Parallel Case -
Feb 28 Lecture 09 Suggested Coding and Design Practices -
Mar 1 Assignment 3 - HW3 Due: March 12th
Mar 04 Lecture - -
Mar 06 Lecture - -
Mar 11 Lecture - -
Mar 13 Lecture - -
March 16 Spring Break Ends on March 24th -
Lecture 10 Operators_Operands_Variables_Literals -
Mar 25 Lecture 11 Synth and Loops -
Mar 25 Quiz 1 -
Mar 27 Lecture 12 FSM I -
Mar 27 Assignment 4 HW4 Prelim: April 3;Final: April 5
Lecture 13 FSM II -
April 1 Lecture - -
April 1 Quiz 2 -
April 3 Lecture - -
April 5 Last Day for Course Withdraw - -
April 8 Lecture - -
April 10 Lecture - -
April 10 Quiz 3 -
April 15 Lecture - -
April 15 Midterm 1 -
April 17 Lecture - -
April 18 Assignment 5 HW5 Preliminary April 23. Final Due April 25
April 22 Lecture - -
April 24 Lecture 14 Parameterized Modules and Simulation, Timing, Testbenches and More Advanced Verilog -
April 29 Lecture - -
April 29 Quiz 4 -
May 1 Lecture 15 Physical Design Flow and Timing Analysis https://eclipse.umbc.edu/robucci/applets/timing_violations/ -
May 1 Lecture 16 Continue Development, FPGA Technology III -
April 25 Assignment 6 HW6 Due May 3
May 3 Assignment 6 Due -
May 6 Lecture 16 FPGA Technology III -
May 6 Practice Quiz Timing Analysis -
May 6 Assignment 7 HW7 Due May 14
May 8 Midterm 2 Exam -
May 13 Final Lecture Design Verification / Final SystemVerilog / Review -
May 13 Practice Quiz Question Programmable Logic Technology (postposed from early semester) -
May 14 Last Day of Classes - -
May 14 Assignment 7 Due - -
May 22 Final Exam 1PM-3PM https://registrar.umbc.edu/wp-content/uploads/sites/31/2024/01/Spring-2024-Regular-Exam-Schedule.pdf -
Previous

Calendar

Date Event Description/Reading Assignments and Due Dates
Aug 30 First Lecture Course Introduction, Intro to FPGAs Reading for Next Class Copyright Elsevier, for class use only
Sept 5 Lecture FPGA Technology I --
Sept 6 Lecture FPGA Technology II use same password as for the reading --
Sept 11 Lecture Introduction Verilog I Introduction Verilog IIIntroduction Verilog III Vivado Installtion, HW1
Sept 18 Due Date Submit HW1 (Submission Instructions Posted on Piazza)
Sept 19 HW2 Assigned HW2 Due Oct 4, simulation instructions
Sept 20 Lecture Events Timing and Testbenches --
Sept 25 Lecture Debugging and Monitoring --
Sept 27 Lecture Full and Parallel Case including Differences in Simulation and Synthesis --
Oct 4 Due Date Submit HW2
Oct 4 Lecture Suggested Coding and Design Practices --
Oct 17 Lecture Details of Operations and Variables --
Oct 5 HW3 Assigned HW3 Due Oct 15
Oct 15 Due Date Submit HW3
Oct 18 Quiz 2 --
Oct 19 HW4 Assigned HW4 Due Oct 25/29
Oct 23 Lecture Synthesis and Loops, Single Assignment Code --
Oct 24 Lecture Case-Statement-Based FSM I --
Oct 25 Due Date Submit HW4 Inital Report
Oct 29 Due Date Submit HW4
Oct 30 Lecture Case-Statement-Based FSM II --
Nov 1 Exam --
Nov 2 HW5 Assigned HW5
Nov 28 Lecture Timing, Testbenches and More Advanced Verilog --
Nov 9 Due Date Submit HW5 initial submission
Nov 19 Due Date Submit HW5 project submission
Nov 20 Due Date Submit HW5 report submission
Nov 29 HW6 Assigned HW6
Dec 4 Lecture FPGA Developement --
Dec 11 Lecture FPGA Tech III --
Dec 11 Due Date Submit HW6
Dec 12 Due Date Submit HW6 report
Dec 13 Final Exam 1:00-3:00 https://umbc.app.box.com/v/fall2018regularfinalexams --
Previous
Date Event Description Assignments and Due Dates
Aug 31 First Lecture Course Introduction, Intro to FPGAs Reading for Next Class Copyright Elsevier, for class use only
Sept 5 Lecture FPGA Technology I Slides *use same password as for the reading
Sept 7 Lecture FPGA Technology II Slides *use same password as for the reading
Sept 12 Lecture FPGA Technology III Slides *use same password as for the reading
Sep 13 Wed Last day to Drop w/o a grade of "W"
Sept 14 Assignment HW 1 Due Thursday Sept 21th
Sept 14 Lecture Introducing Verilog HDL
Sept 26 Assignment HW 2 Due Tues Oct 5th
Sept 28 Lecture Events, Timing, Teshbenches
Oct 3 Lecture Debugging and Monitoring
Oct 3 Lecture Full and Parallel Case Differences in Simulation and Synthesis
Oct 6 Assignment HW 3 Due Fri Oct 13th
Oct 10 Lecture QUIZ
Oct 10 Lecture Slides Suggested Coding and Design Practices
Oct 17 Lecture Slides Details of Operations and Variables
Oct 18 Assignment HW 4 Preliminary Design Report Due 25th, Final Submission Oct 27.
Oct 26 Lecture Slides Synthesis and Loops, Single Assignment Code
Oct 24 Lecture Slides Synthesis and Loops
Nov 2 Lecture Slides FSM I
Nov Assignment HW 5 Preliminary Design Report Due Nov 10, Final Project Submission Nov 15.
Nov 7 Midterm Exam
Nov 9 Lecture Slides FSM II
Nov 20 Quiz topics related to procedural blocks and statemachines
Nov 21 Lecture continue state machines
Nov27 Assignment HW 6 Due Dec 4th
Nov 28 Lecture Timing, Testbenches and More Advanced Verilog
Dec 5 Assignment HW 7 Due Dec 12th NO LATE SUBMISSION
Dec 5 Lecture FPGA Developement
Dec 13 Wed Study Day
Dec 14 ThursFinal Exam Time: 1:00 - 3:00 Final Exam Schedule

Reading and References


Provided Materials

Vivado TCL

proj.tcl My first Vivado Non-Project Mode Tcl Script edited from Xilinx UG892

Test Bench example with File IO

Advanced Test Bench Examples

Soft Processor Cores

Example Pattern State Machine


Assignments

Previous

HW1

Assigned: Thurdsay 2016/02/04
Due: Thursday 2016/02/11 24:00
HW 1
Submission instructions have been sent by email.
Submit the following:
1. A bitmap screenshoot (i.e. PNG file) of your Schematic
2. Your user constraints file (UCF)
3. The Verilog files for blocks in your schematic
If for some reason you cannot submit the schematic screenshot by tomorrow (Xilinx tools not accessible) please email it to me as soon as possible.

HW3

Assigned: 2016/02/25
Due: Monday 2016/03/04 at midnight
Assignment PDF
The TA's will distribute the points to the questions based on the difficulty and effort required to answer the questions. A distribution will be posted soon. Use the submission system to post to the hw3 folder. Late policy 20% for one day late and zero thereafter. Late homeworks should be posted to hw3_late.

HW3

Assigned: Fri 2017/10/06
Due: Fri 2017/10/13 at midnight
The assignment: HW3:Light the Candles
debounce_and_oneshot.v
top.ucf just something for reference, read board manual and edit as needed
point distribution will be discussed in class
Repo: git clone USERNAME@gl.umbc.edu:/afs/umbc.edu/users/r/o/robucci/pub/cmpe415/submit/hw3/cmpe415_hw3_USERNAME

HW3

Assigned: 2010/09/22
Due Next Tues at midnight. 2010/09/18
You must show work with code and simulation results as appropriate.
You must provide testbenches to validate any any code written.
You must comment code.
You will only turn in a PDF
From Chapter 4 of the book:
7 a
7 b Repeat b four times as follows:
I) using behavioral code with if statements
II) using concurrent assign statement(s)
III) using primitives
IV) by creating a User Defined Primitive
13
16 a,f,g,h,i,k,l,n,o,p,r,s,t (read chapter and/or run code to find answers as needed)
17
19
22
26
27

HW4

Assigned: Wed morning 2010/03/10
Due Friday at midnight. 2010/03/25
lab4_Paddle-Ball-Game.pdf
For reference:
pulser.v
random2.v
rotator_oneshot.v
top.ucf for reference, read board manual and edit as needed

HW5

Assigned: Tues 2016/03/29
Due Wed 2016/04/06 before class: state-machine and top-level system diagram. (5 pts)
Due Friday 2016/04/08 before midnight: Project Submission.
Due Friday 2016/04/09 before midnight: Report which should include the final state machine and top-level system diagram.
lab5_Paddle-Ball-Rounds.pdf
LCDDriver.v
(still seems a little glitchy sometimes, but usable)

HW7

Due Last Day of Semester Classes by midnight. 2016/05/10
hw7.pdf

HW6 OLD!!!

Assigned: Tuesday 2010/10/19
Due Next Tuesday before class. 2010/10/26
HW6.pdf
show all work, including code, in PDF

Final Project

'''Final Project''' Due The last Day of Classes..Dec 13. Check for updates. The final project will be graded based on successful completion and presentation of FPGA-based project. Students need to be able to identify the challenges of the design, document solution approaches, evaluate the success of the design, and make recommendations for further approaches for improvement. The grade will be based on the execution of the work, performance of the design on an FPGA, but also a presentation in written and/or oral form.
Groups of about 3 should have chosen a project. Each student must complete a portion of the coding that is equivalent to around a 1 1/2 week HW. This will be approved by the instructor. Each student will be responsible for creating test benches and reporting testing results to the team for their parts. The team will then work together to integrate the pieces, make corrections, and demonstrate the final operation. Each lab member must generate a comprehensive report including the project goals, the design approach, design decisions, description of design and reporting of testing of the all main parts (each student must report on all parts), issues encountered in integration and any corrections that needed to be made. More guidelines on the final report may be provided.
Nominal Grading unless provided otherwise:
50% Hardware demonstration successful. (common grade)
20% Personal coding: coding, commenting and documentation for your part, design and usability
10% Operation and Testing of your part (includes the testing, the reporting and evaluation of it)
10% Report evaluation of the following: the design, performance, use, and testing of other team members' parts. Be insightful and honest: describe what was good and bad. Was the interface good? Was enough testing done so that you were confident in the part? Did it work? Did it work as described or as you thought? etc...
10% Description of project, the pieces and interfaces, the process and experience especially including integration and interface challenges, and the successes and failures.