Lecture 00 – Introduction to Programmable Devices

• An FPGA is a type of Intergrated Circuit (IC)

  • In-class show-and-tell:

    • FPGA Board with Packaged IC with Heat-Sink
    • FPGA Board with Packaged IC
    • Packaged IC with Open Cavity, exposed
      • Die
      • Bond Wires
      • Bond Pads on Die (too small to see)
      • Bonding sites on pakage
    • FPGA Silicon from the silicon up http://www.righto.com/2020/09/reverse-engineering-first-fpga-chip.html
• A Field Programmable Gate Array is an IC that is
  • typically re-programmable as opposed to one-time programmable
  • Field/In-system programmable (ISP): can be programed in the system rather than in a separate programmer HW
• Can implement various logic including…
  • Misc. or "glue" logic between systems
  • Full ASIC replacement..esp. valuable if ASIC is no loger manufactured
  • Digital Signal Processor - via custom logic and/or in-built DSP cores
  • Microcontrollers - implemented as a customizable soft processor (e.g. RISC-V)or using an fixed in-built hard processor (e.g. ARM)
  • High-speed communications (physical layer)
  • Reconfiguralble computing (adaptable hardware-accellerated behaviour)

• Field (-programmable)
  • In-field programming / in-place programming , in-system programming
    • can be reprogrammed even after being placed on board, can be programmed without disassembling the board

    • does not require complex programming hardware such that it can only be done at a factory

      ❌ unessisary programmers

      

      -- Jcl365, Public domain, via Wikimedia Commons

      

      -- DPJessie, CC BY-SA 4.0 via Wikimedia Commons

    • supports in-system feature upgrades after a product is sold, shipped, and deployed Found in MacBook: https://www.ifixit.com/Teardown/MacBook+Pro+15-Inch+Unibody+Early+2011+Teardown/4990

• Programmable
  • After physical design and manufacturing, it can be reconfigured to perform many functions and satisfy needs for many applications
    • As opposed to an ASIC (application specific integrated circuit) a custom ic designed for one application/function
  • A distinction between one-time programmable and reprogrammable should be noted.
  • Most FPGAs using SRAM cells for configuration memory, naturally providing capability for fast reprograming
  • Other devices may use fuse technology that can be “burned” once and thus are one-time programmable.
  • Some devices may use “flash” type memory design to be reprogrammable
    • mutiple time but not as many as a SRAM device.
• Gate Arrays
  • Arrays of logic gates
    • and,or,xor,nand, etc…
    • muxes, 1-bit adders
    • registers,latches
    • Lookup Tables (LUTs)
  • also DSPs, Processor Coress, GHz serializers,etc…

http://www.xilinx.com/company/gettingstarted/fpgavsasic.htm

• FPGAs have a shorter design process and shorter design cycles
• When problems arise, design iterations are required that can be very time-consuming.
• FPGAs have a significant advantage when design updates are required based on in-system testing

• Updates in-field allows in-system test and re-programming; insertion of new debug circuitry and later removal; and feature upgrades

  Design-Test Iterations: Left: minutes/hours/days/months depending on scope ; Right: months

• FPGAs
  • require some extra board infrastructure versus an ASIC
    • such as a programming interface, configuration memory, multiple power supplies
  • are more expensive at high-volume versus an ASIC
  • ASIC can be designed for various needs of a system
    • FPGAs cannot facilitate exotic, custom system-on-IC circuit combinations
      • Ex: can't have custom RAM+DAC+DSP+RF modulator+ sensor interface (though FPGAs are getting more and more features to suit demands)
  • Power: a microcontroller that is good fit for small computational needs will often consume less power, and given enough time ASIC can always be design to be more power efficient
  • Routing (data communication and clock) power is significant in ICs and particularly expensive in FPGAs since the functional logic density is less than an ASIC and thus designs are more spread out, techniques for low-power clock network customization are limited
  • FPGAs have may have many unused internal components adding leakage current and power
•  In spite of shortcommings, using an FPGA means capitalizing on others' high-level work (hardware designs and tools) meaning they may still be optimal given a constrained design time or time to market.

• Discrete ICs, Gate-Level: quad-and, quad-or, hex-inv, 4-bit register, etc..
• PLDs (Programmable Logic Devices): think simple and-or array unit that can implement multiple sum of product terms
• CPLDs (Complex programmable Logic Devices): think larger&more simple and-or combination units and interconnections
• FPGAs: a veriety of mentioned units and very complex and versatile interconnections/routing

• Non-recurring engineering (NRE) cost:: "refers to the one-time cost to research, design, develop and test a new product or product enhancement." (source: https://en.wikipedia.org/wiki/Non-recurring_engineering)
• Time-to-Market
  • product late to market miss sales, can suffer long-term adoption penalties, and benefit competitors

(gate arrays are less common now)

• HDLs serve in multiple roles including
  • "netlist description" — replaces graphical schematic entry or representation as "fuse maps" (discussed later)
    • provides standardization and facilitates automation in complex tool flows that is not achieved with schematics
  • "behavioral descriptions" : models that are abstracted from circuit implementation and can serve as design specifications
  • simulation and verification — HDL models can be simulated, and HDLs provide additional syntax to specify simulation and verification processes
• Manual programmed connection/value is (.e.g fuse maps) is not practical for the scale of FPGA Designs
• Hardware Design Languages (HDLs) are the core to most FPGA design flows
  • Verilog and VHDL are the predominate languages
• Compared many standard programming languages, HDLs also offer
  • modeling of hardware parallelism through concurrency
  • features and syntax to model evolution of time, i.e. delays
• Circuit designs are synthesized from HDL code and mapped to available resources on and FPGA, followed by place-and-route
• A bitstream is generated that can be used to configure the FPGA

• Structural
  • Structural code is basically a text version of a schematic
  • Structural code defines instantiations and connections of primitives
  • primitives defined by simple inbuilt operators, behavioral code, switch-level models
• RTL
  • implicitly defines existence of registers (sequential logic) and the combinatorial logic functions between them
  • regarded as "synthesizable" code
• Behavioral
  • Describes function, often at highest level of abstraction
  • May or may not be synthesizable
  • Non-sythesizable code is for modeling an simulation
    • examples of non-synthesizable constructs:
      • arbitrary delay
      • Disk file IO typically during simulation

module  adder1bit(sum,cOut, a,b,cIn)
  input a,b;
  output wire sum,cOut; 

  ...<instantiate and/ors/xors/etc>...

endmodule


module adder8bit(sum,cOut, a,b,cIn)
  input [7:0] a,b;
  output wire [7:0] sum,cOut;

  ...<instantiate 1-bit adders>...
endmodule

module adder(sum, cOut a,b,cIn); 

input [7:0] a; 
input [7:0] b; 
input cIn;
 
wire [8:0] result;
 
output [7:0] SUM;
output cOut 
 
result = A + B + CI;
assign sum = result[7:0];
assign cOut = result[8]; 
endmodule 

module ALU(  result, a,b,op); 

input [7:0] a; 
input [7:0] b; 
input op;

output logic [8:0] result;
  
always_comb begin
   if (op==1) begin
       result = A+B;
   end else begin
       result = A*B;
   end
end

endmodule 

We will discuss the distinction of RTL and Behavioural extensively in this course.

• in the world of FPGAs, SoC (System-on-a-Chip) commonly refers to use of traditional FPGA design along with a general-purpose processing core executing software
• May be a fixed hard-processor (could look at the silicon and see it) or a customizable soft-processor
• A software-executing processor needs code-developed code to run
  • integrated (code) development environment (IDE) is provided along with the FPGA tools.
• Mixed with other processing/memory/communications design cores, called IP Core​s or IP​s

• A soft- or hard-processor facilitate running traditional sequential code
• A Soft Processor is a compiled, customizable processor (not to be confused with fixed processors sometimes provided on FPGAs)
  • cannot be seen by looking at the FPGA silicon
• examples of options and parameters:
  • cache size, #bits,
  • on-FPGA RAM,
  • external RAM controller
  • branch prediction…
• Some offer even more features typical
• on microcontrollers like
  • SPI (serial peripheral interface)
  • pulse width modulators
  • Custom instructions
    • hardware accelerate frequently executed code
• IDE provides
  • editor,
  • debugging gui,
  • on-chip debugging, variable monitoring
  • code alteration, and execution control
  • Advanced features like on-the-fly hardware break-points depend on processor configuration

• Most basic user interface is a terminal hosted on PC but interaction with host software written in Python, C++, Matlab, Labview, etc.. is common too.
• USB, USB-JTAG, and Ethernet would be the most typical conduits

• Whereas previous FPGA developent software approaches considered a processor as one component in a design, modern approaches view the processor as the central element and additional logic as an addon
• Emphasiszes SOC,
  • Processor and IP-Centric Design (maximaly using pre-built cores)
  • co-development of C/C++ (soft procesors) and other IP-based design

• FPGAs are customizable: tend to be more useful when a multitude of various specialized operations are required that are NOT implementatble an a few traditional processor instructions
  • (may consider bit reordering)
• FPGAs can exploit parallelism at a low-level well beyond what general-purpose processors can do, achieving high utilization to implement complex operations
• FPGAs can implement many parallel operations with well-defined timing
• GPUs leverage parallelism, and have proven themselves for parallism of traditional instructions like multiply-accumulate for machine learning applications
• The advantage of low-cost FPGA parallelism is limited when large memories are involved that nessicitate the of use of external memory and memory-transfer-limited processing (memory-bound vs compute bound)
• As ASIC designs become comparatively more expensive FPGAs have displaced them in some markets
• Notable is
  • Intel’s acquisition of Altera (and recent separation) and
  • AMD aquisition of Xlinx
  • Amazon offering FPGA cloud computing
  • Microsemi aquired by Microchip
• Understanding FPGA technology and how to integrate then in complex CPU-GPU-FPGA-DRAM-Flash computing systems is a marketable skill
  • learning required for FPGA design also represents learning many marketable skills including digital system design as well as design and verification using HDLs

https://covail.cs.umbc.edu/nextcloud/s/9Xa3YCXjP4iMNBm

• REPROGRAMMABLE
• FPGA
• ASIC
• JTAG
• BITSTREAM
• SOFT-PROCESSOR
• IP Core
• HDL
• GLUE LOGIC
• CPLDs
• DIE
• PACKAGED IC
• FPGA BOARD
• Verilog
• VHDL

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