L01 FPGA Technology I

Prof. Ryan Robucci

References

• † Some slides (blue-frame) developed by Jim Plusquellic
• ‡ Some images credited from Book: Maxfield, Clive. The design warrior's guide to FPGAs: devices, tools and flows. Elsevier, 2004.

History

• Origins of FPGAs
• Xilinx introduced first FPGA in ’84, but engineers didn’t embrace them until early ’90s.
• History:
  • ’47: Shockley, et. el. introduce first transistor at Bell Labs.
  • ’50: Bipolar junction transistor (BIT) introduced.
  • ’62: Hofstein, et. el. introduce metal-oxide semiconductor field-effect transistor (MOSFET) at RCA.
  • ’58: Jack Kilby introduced the integrated circuit.
    • (Jack Kilby, Nobel Prize winner, 2000)
  • ’70: Intel introduced 1024-bit DRAM, Fairchild introduced 256-bit SRAM.
  • ’71: Intel introduced first microprocessor, 4004.

Family of Programmable Dev.

• Programmable Logic Device arrived in 70’s and but only end of the 70’s did more complex variations emerge
• New complex variations were called complex PLDs (CPLDs) while the original line became known as SPLDs

Programmable Logic

• Here, the data on input line may be used or not.
  • If it is not used it is pulled to "1"
    • this value is the AND identity, so it has no effect on the output.
  • If the line is used, the pull-up to "1" is overridden by the driven value
    • assumes input driver is much stronger than the pull-up resister
• Try to configure switches to implement not a and b:
  

Programmable Device Technology

• We’ll now discuss technology for implementing the switches….

Fuses

• A fusible-link technology is required to implement links as fuses
• All links are initially active and must be selectively removed
• One-time programmable --- fusible-link-based devices are one-time programmable unless...
• twice-programmable if a redundant fuses or devices are provided to provide a second bank of programmable devices
• Fuses are burned selectively by applying large voltages

Anti Fuse Technology

• All links are initially inactive and must be selectively added.
• Links are implemented are implemented as insulators that are destroyed or changed such that a conducting path is realized.
• There are one-time programmable unless redundant devices are provided.
• No need to programed unused sections of IC

Mask-Programmable Technology

• Most layers are predesigned and prefabricated, requiring a minimal number of custom layers and masks per new design.

Memory as Logic --- Look up Tables (LUTs)

• Mask programming was used to create memories known as a ROM (read-only memory). This is shown in the next figure.

• Memory can mimic the behavior of an arbitrary circuit by effectively storing the circuit's truth table and recalling entries using the inputs as the address (index) into the table.

• Description of a circuit:

  y = a xor b xor c
  u = ((a and b) or 
       (a and c) or 
       (b and c) )
  v = a and b and c
  

• Truth table:

  Address (input)	Stored Data for ouput
  abc	yuv
  000	000
  001	100
  010	100
  011	010
  100	100
  101	010
  110	010
  111	111

2D Data Store

• Now for the piece needed to select a row based on the input....

Example with fuse technology:

Decoder

• Functional schematic of decoder:
• (actual circuitry may differ,e.g. wired and may be used):
  
  

Metal Mask LUT

• Transistors are same, but metal layer is added
• Can en mass prefab wafers except top metal and added it later

Wired OR Outputs (Active Low Output in this example)
Conceptually the same as the following:

Wired-OR Logical Depiction

Common Logical depiction style for programmbale wired OR:

Fuse/Anitfuse Link

• No need to re-manufacture mask and incur fab costs and time with every change.
• To change design, throw IC out and "burn" another.
• Even better case is being able to "erase" programming on IC and reuse it...

Symbols for Unconnected/Connected:

Floating Gate Transistor

• Left: A positive potential at the gate input turns transistor on by using capacitive coupling to collect charge to form a channel

• Right: The input influences channel through a series capacitance, but a stored potential on the floating gate has an effect too.

• Total effect is that of input through series cap + effect of stored potential.

  • Negative charge storage prevents channel formation.
  • Positive charge storage assists channel formation.
  • Floating-Gate PFET works opposite Floating-Gate NFET

• Depending on design, and stored charge a floating-gate fet can be set to

  • switch on and off with the input, or
  • it can be set to be always-on or always-off regardless of the input.

• Here are two ways to design a programmable switch cell:

  • The second one uses two FETs...including the space between them it was about 2.5 times larger.
    

Floating Gate LUT

• Only stored charge is different.
  

• Nothing in manufacturing sets function.

• Charge stored on "floating" node determines transistors function.

• Charge can be changed by electric fields and UV light....next slide.

• No need to re-manufacture mask and use fab every time, or even get a new IC. To change design, just "erase" IC and reprogram it.

• Opportunity for in-system programming (ISP) and in-the-field updates (field programmable).

EPROM and EEPROM

• EPROM - Erasable Programmable ROM.
  • This refers to the fact that with normal operating voltages it
    functions as a ROM, but UV light can be used to erase it (around 20 minutes).
  • Cells typically implemented using single FET. order of magnitude smaller than fusible links -> better density
• EEPROM (E2PROM)- Electronically Erasable programmable ROM.
  • This refers to the fact that with normal operating voltages it functions as a ROM, but special high voltages can be used to erase it.
  • Cells typically implemented using two-FET design, thus it is typically larger than EPROM.
• Fundamental structure and operation are same.
• Difference in details of material, dimensions, and spacings to allow for UV or electronic erasing and proper capacitive couplings.
  

SRAM

• Typically larger than EEPROM cell

• Electronically Erasable

• VERY fast reprogramming

• Volatile

• 1 or 0 Stored in each latch
  

  :::borrowed (SRAM transistor image is public domain by Inductiveload, sourced from wikipedia)
  
  :::

• Most FPGAs use SRAM

• Fast reprogramming

• SRAM is an extremely common building block in IC design, this means the structure will be well tested and sure to be reliable in most any technology

• Can be implemented in standard CMOS fabrication technology without need for extra layers or processes for special materials that significantly increase cost

• Volatile...must be reprogrammed at powerup

  • System needs may demand a non-volatile configuration memory on-board (not fuse and flash technologies store the configuration as non-volatile on-chip)
    
    • *A security concern is that a design is transferred as a data stream at boot..it should be encrypted if IP theft is a concern

• Programming is fast, it can support dynamic reconfiguration were hardware is reconfigured on-the-fly during operation to accelerate functions on-demand

Antifuse

• One-time programmable (unless redundant fuses are provided to provide twice-programmable)
• Radation hard – not as susceptible to radiation induced “bit flips” that alter configuration in SRAM
  • In particular SRAM is most susceptible as data is being loaded, during programming

Flash

• Was about 2.5 times larger cells than EPROM, but still smaller than SRAM
  • Note area impacts logic delay and power
• Dedicated flash processes require ~5 additional process steps
• Flash technology integrated with logic is has not quite as rapidly updated as SRAM on newer, smaller technology nodes
• Vulnerable to long-term effects from Radiation
• “Hybrid flash/SRAM” can use local flash to store configuration and SRAM to implement switches

Programmable Element Technology Overview

:::borrowed Maxfield, Clive. The design warrior's guide to FPGAs: devices, tools and flows. Elsevier, 2004.

Feature	SRAM	Antifuse	E2PROM/FLASH
Technology node	State-of-the-art	One or more generations behind	One or more generations behind
Reprogrammable	Yes (in-system)	No	Yes (in-system or offline)
Reprogramming speed (inc.. erasing)	Fast	---	3x slower than SRAM
Volatile (must be programmed on power-up)	Yes	No	No (but can be if required)
Requires external configuration file	Yes	No	No
Good for prototyping	Yes (very good)	No	Yes (reasonable)
Instant-on	No	Yes	Yes
IP Security	Acceptable (especially when using bitstream encryption)	Very Good	Very Good
Size of configuration cell	Large (six transistors)	Very small	Medium-Sized (two transistors)
Power Consumption	Medium	Low	Medium
Rad Hard	No	Yes	Not Really

:::

PROM

• Implements sum of products
• Built from TWO arrays:
  • Fixed AND gates (example uses 3-input ANDs )
  • Programmable OR gates (variable 1 to 8 inputs)
• For the fixed AND array, all inputs outputs must be fabricated since you don't know which product terms are needed. (8 gates required for exhaustive cover for 3 inputs), whether they are wanted or NOT (i.e. some go unused)
• For programmable OR portion, the programmer can decide which terms are wanted
• The number to fabricate in silicon is decided based on past experience of the manufacturer while the number to actually wire is decided by the programmer.

Left: Fixed, exhaustive prewired AND Array
Right: Programmable, typically non-exhaustive OR array

:::borrowed

:::

:::borrowed Plusquellic, J.

:::

• As you know from previous courses, any truth table can be translated to a Boolean sum of products or product of sums.

PLA

• Implements sum of products
• Built from TWO programable arrays
  • Programmable AND gates (example uses 3-input ANDs )
    • flexibility offered by programmablity allows for a non-exhaustive AND Array with selected products
  • Programmable OR gates (variable 1 to 8 inputs)
    • flexibility offered by programmablity allows for a non-exhaustive OR Array with selected sums
• For the programmable AND array, not all inputs outputs must be fabricated. The number decided by the manufacturer sets how many product terms can be implemented
• The downside is that programmable technology tends to be slower...PLAs were never significant

PALs and GALs

• Programmable Array Logic

• Implements sum of products

• Built from two arrays in opposite approach of PROM:

  Left: Programmable non-exhaustive AND array
  Right: Fixed (predefined), typically non-exhaustive OR/NOR array

• Introduced in late 70s to address speed problems with PLAs.

• Since second array is not programmable it was designed to be faster.

• Downside compared to PLAs is the limited number of terms that can be OR’ed (illustrated is only two at a time)

• GALs: Lattice Semiconductor '84, offered electronically erasable varient of PALs called Generic Array Logic that

More Complex Devices

• Real devices supported additional features

  • Programmable Output Inversion
  • Tristable Outputs (useful for buses and wired-or logic)
  • Ability to latches outputs
  • Configure pins as input or output (useful on smaller packages with limited physical pins)

• CPLDs replaced PLDs (which became known as SPLDs)

  • Were essentially multiple SPLDs
  • on a chip but a key new enable technology was programmable interconnect (by Altera)
  • Introduced in ‘84 by Altera (now Intel) based on CMOS and EPROM technologies

Cost of Interconnect on Complex Programmable ICs

• CPLDs would have many simple programmable interconnected connected

• As more blocks are added, exhaustive or fixed % global interconnect grows rapidly > O(n), in area, average delay, power...
• Less percentage of IC was “logic” and more was interconnect

(depicted as 1-D array for simplicity)

• A replacement for exhaustive interconnect was critical...

CPLDs / FPGAs

• programmable muxes/interconnect allowed for fewer routing lines amoung devices while maintaining a versitle connectivity choices
  • (don't need on the order of $(\#outputs\,per\,block) \times (\#blocks)^2$ connections)

(depicted as 1-D array for simplicity)

• a large 2D array of devices with local and global routing options
  

PALASM, JEDEC, etc..s

:::borrowed Plusquellic, J.

:::