Lecture 07 – Debugging and Monitoring Statements

  `timescale 1ns / 1ps 
  module and_tb;   // Design Unit Testbench
    parameter STOP_TIME = 10000;
    reg [3:0] a;
    wire      y; 

    // Instantiate DUT 
    and I1 (y,a[3],a[2],a[1],a[0]); 
    initial begin // Create DUT stimulus generator with print
        #10; 
        a = 4'b1100; 

        #10; 
        $strobe ($time,"%0t:$strobe1 a = %b y = %b", $time, a, y); 
        $display ($time,"%0t:$display1 a = %b y = %b", $time, a, y); 
        a[0] = 1'b1;
        $strobe ($time,"%0t:$strobe2 a = %b y = %b", $time, a, y); 
        $display ($time,"%0t:$display2 a = %b y = %b", $time, a, y); 
        a[1] = 1'b1; 
        $strobe ($time,"%0t:$strobe3 a = %b y = %b", $time, a, y); 
        $display ($time,"%0t:$display3 a = %b y = %b", $time, a, y); 
     end // initial begin 
  endmodule // and_tb
  #end_src



#+begin_src result
                  2020000:$display1 a = 1100 y = 0
                  2020000:$display2 a = 1101 y = 0
                  2020000:$display3 a = 1111 y = 0
                  2020000:$strobe1 a = 1111 y = 1
                  2020000:$strobe2 a = 1111 y = 1
                  2020000:$strobe3 a = 1111 y = 1

module (...)
  inv1 M1(a,b);
  inv1 M1(c,d);
endmodule
module inv1(y,x);
output y
input x;
 always @ (x) begin
   $display(“Instance %m is doing something”);
 end
endmodule

my_block M1 (a,b,c);
$monitor(M1.I1.my_procedure.count);

module fw_test;
 initial begin:block1 //naming a block allows 
                       //creating local variables
    reg [31:0] fd1;
    reg [7:0] x;
    x = 8'b1;     
    fd1 = $fopen("output.txt"); //default mode 
                                //  is overwrite   
    if (fd1 == 0) begin
      $display("file open error");      
      $finish();      
    end
    $fdisplay(fd1,"x:"); //without a formating string
    $fdisplay(fd1,x); //without a variable
    $fdisplay(fd1,"display:%08b",x);
    $fwrite(fd1,"write:%08b",x);
    $fstrobe(fd1,"strobe:%08b",x);
    #1 //required last time advance to make strobe 
       // output before file close
    $fclose(fd1);
 end
endmodule // file

x:
  1
display:00000001
write:00000001strobe:00000001

module adder(sum,a,b,en,clk);

   output logic [7:0] sum;
   input [7:0]        a,b;
   input              en;
   input              clk;


   always @(posedge clk) begin
      if (en) sum <= a+b;
   end

endmodule // adder

module adder_tb;

   logic clk;
   logic [7:0] sum;
   logic [7:0]        a,b;
   logic              en;
   adder DUT (.*);

   wire data_out;
   reg [3:0] addr;
   reg [15:0] input_buff [0:7]; // 8 entries each of 16-bits
   integer   idx;
   integer   file;

   initial begin
      clk = 0;
      forever #10 clk = ~clk;
   end


   initial begin
      //$monitor($time,"a:",a," b:",b," sum:",sum);
      $readmemh("memory_hex_in.txt", input_buff); //init input_buff from file
      file = $fopen("memory_hex_out.txt");  //open a file for writing results
      @ (posedge clk);
      en <= 0;
      for (idx=0; idx<8; i++) begin //write to mem
         @ (posedge clk);
         en <= 1; {a,b} <= input_buff[idx];
         @ (posedge clk);
         en <= 0; {a,b} <= '0;
         @ (posedge clk);
         //$strobe(sum);
         $fstrobe(file,"%2H",sum);
      end

      @ (posedge clk);
      $fclose(file);
      $finish;
  end
endmodule

a1
a2
a3
a4
a5
a6
a7
a8

wire data_out;
reg write;
reg [3:0] addr;
reg [7:0] memory_buffer [0:15]; // 16 entries 8 bit #'s 
reg [7:0] data_in; 
integer i; integer file; 
my_mem DUT (data_out,data_int,addr,write);
initial begin
    $readmemh("memory_hex_in.txt", memory_buff); //init memory_buff from file
    file = $fopen(“memory_hex_out.txt”);  //open a file for writing results
    #5 write <= 0; addr <= 0;
    for (i=0; i<16; i++) begin //write to mem
        #5 write <= 0; data_in <= memory_buff[i]; addr <= i;
        #5 write <= 1;
    end
    #10 write <= 0;

    //reading and writing to file
    for (i=0; i<16; i++) begin  
        #5 addr <=i;
        $fstrobe(file,“%2H”,data_out);
    end
    $fclose(file);
end