Date | Event | Description | Assignments and Due Dates |
---|---|---|---|
Aug 31 | First Lecture | Course Introduction, Intro to FPGAs | Reading for Next Class Copyright Elsevier, for class use only |
Sept 5 | Lecture | FPGA Technology I Slides *use same password as for the reading | |
Sept 7 | Lecture | FPGA Technology II Slides *use same password as for the reading | |
Sept 12 | Lecture | FPGA Technology III Slides *use same password as for the reading | |
Sep 13 Wed | Last day to Drop w/o a grade of "W" | ||
Sept 14 | Assignment | HW 1 Due Thursday Sept 21th | |
Sept 14 | Lecture | Introducing Verilog HDL | |
Sept 26 | Assignment | HW 2 Due Tues Oct 5th | |
Sept 28 | Lecture | Events, Timing, Teshbenches | |
Oct 3 | Lecture | Debugging and Monitoring | |
Oct 3 | Lecture | Full and Parallel Case Differences in Simulation and Synthesis | |
Oct 6 | Assignment | HW 3 Due Fri Oct 13th | |
Oct 10 | Lecture | QUIZ | |
Oct 10 | Lecture | Slides Suggested Coding and Design Practices | |
Oct 17 | Lecture | Slides Details of Operations and Variables | |
Oct 18 | Assignment | HW 4 Preliminary Design Report Due 25th, Final Submission Oct 27. | |
Oct 26 | Lecture | Slides Synthesis and Loops, Single Assignment Code | |
Oct 24 | Lecture | Slides Synthesis and Loops | |
Nov 2 | Lecture | Slides FSM I | |
Nov | Assignment | HW 5 Preliminary Design Report Due Nov 10, Final Project Submission Nov 15. | |
Nov 7 | Midterm Exam | ||
Nov 9 | Lecture | Slides FSM II | |
Nov 20 | Quiz | topics related to procedural blocks and statemachines | |
Nov 21 | Lecture | continue state machines | |
Nov27 | Assignment | HW 6 Due Dec 4th | |
Nov 28 | Lecture | Timing, Testbenches and More Advanced Verilog | |
Dec 5 | Assignment | HW 7 Due Dec 12th NO LATE SUBMISSION | |
Dec 5 | Lecture | FPGA Developement | |
Dec 13 Wed | Study Day | ||
Dec 14 Thurs | Final Exam | Time: 1:00 - 3:00 Final Exam Schedule |