// Verilog Test Fixture Template // simulates write and read `timescale 1 ns / 1 ps module my_ser_mem_tb; reg clr,clk,sdi,read,write; wire sdo; my_ser_mem dut1 (sdo,clr,clk,sdi,read,write); //reg [3:0] mem [7:0]; //memory is eight four-bit words //reg [1:0] read_send_index; //not reg //reg [2:0] addr; //reg [2:1] addr_index; //reg [7:0] NS; //not reg //reg [7:0] CS; //reg sdo; //not a reg //wire [3:0] word_to_send; //extra register??? //reg write; //not a reg initial clk =0; always #10 clk = ~clk; initial begin clr= 1; read = 0; write = 0; #100; clr = 0; //write #200; write = 1; sdi = 1; #20; sdi = 1; #20; sdi = 1; #20; sdi = 0; #20; sdi = 0; #20; sdi = 1; #20; sdi = 1; //read #200; read = 1; sdi = 1; #20; sdi = 1; #20; sdi = 1; #200; $finish; end endmodule