image/svg+xml
These are the drawings that the symbols are created from.
Note that each drawing has a “none” line around it that is on grid.
This allows the symbols to be easily moved on grid once placed.
The grid is 1/32 of an inch.
A main focus of the orginal symbols is on compactness.
Note: Sometimes for drawing I temporarily switch to 1/64 grid.
Add symbols with unique names and share all.
I rounded many line ends and joints using line options
I left space in the middle for text.
Path => CombineAdd linked offet, immediatly set it to have stroke but no fillReselect the source path, set it to have fill and no stroke and send it behind linked path
Init/RA2/WA2
RA1
RA0
SD0
SD1
SD2
SD3
a2
a1
a0
d3
d2
d1
d0
clk
sdo
read
sdi
write
ts1
ts1 is some time requirement for data and read or write signal to arive before the clock - very littleth1 is the time required for data to be held after the clock signal - very littletp1 is the time after the clock that data becomes available - smallth2 is the time after the clock that the data is guaranteed to be held - 0
th1
th2
tp1
sdo
sdi
write
read
CMPE 415Serial MemoryExample
word to write upper bits
word to write
address
address index
write bit index
address
3
1
sdi
an enable
an enable
selected word
4
an enable
send bit index
sdo
Eight4-bit wordregister
WA1
WA0
WD0
WD1
WD2
WD3
a2
a1
a0
d3
d2
d1
d0
sdo
sdi
write
read
Init/RA2/WA2
Init/RA2/WA2
Init/RA2/WA2
"new" high values initiate reads
no second read is initiated here
"new" high values initiate writes
no second write is initiated here
Read
Write
Sketch of initial design for registers and data-flow