Pre- and Post-Synthesis Simulation Vivado

This is a supplementary document for HW2.

Create a project with a Verilog file as the top module (no need for top-level Schematic):

For Simulations with the GUI, create a new project as before starting with menu File-> Project New

On HW1, we used a schematic for the benefit of a visual depiction, but you will want to avoid this going forward and learn use Verilog files directly as your top level design file.

After adding/creating a Verilog file using menu File->Add Sources... (Control-A) as shown in HW1, you can make any file the top-level Design Source File. To do this perform the following:

Find the the file in your "Sources Window" , for example if you named it top.v

• Design Sources
  • top (top.v)

Right-click the file and select "Set as Top". It should become bold

• Design Sources
  • top (top.v)

Create a Simulation Testbench:

File->Add Sources... (Control-A)

Select "Add or create simulation sources" and click Next>

[Create File]

• File type: Verilog
• File name: top_tb.v
• File location: Choose Location...

Click Finish

Define Module:

A testbench has no pins, just click OK and Yes to the pop-up dialog

Find the top_tb.v file in your "Sources Window," e.g.

• Simulation Sources
  • sim_1
    • top_tb (top_tb.v)

Right Click top_tb.v and select "Set as Top" . It should become bold in the Simulation Sources tree, leaving top.v bold under the Design Source Tree.

• Simulation Sources
  • sim_1
    • top_tb (top_tb.v)

you can now edit top_tb.v by first instantiating your top module and providing the necessary test-bench code

Finally, to run a simulation use menu Flow -> Run Simulation

• Select One of the following depending on problem:
  • Run Behavioral Simulation
  • Run Post-Synthesis Timing Simulation
  • Other options are not used at this time
    • Run Post-Synthesis Functional Simulation
    • Run Post-Implementation Functional Simulation
    • Run Post-Implementation Timing Simulation