**Course Title** : Reconfigurable System Design
**Course Number** : CMPE 691
**Credits**: 3.00
**Description**:
**Prequisite ** : Courses covering C, HDL, FPGA
**Instructor**
Dr. Ryan Robucci
** Teaching Assistants and Graders ** : none
**Syllabus** : PDF
**Course Number** : CMPE 691
**Credits**: 3.00
**Description**:
**Prequisite ** : Courses covering C, HDL, FPGA
**Instructor**
Dr. Ryan Robucci
Assistant Professor
Email: robucci@umbc.edu
Department of Computer Science and Electrical Engineering
University of Maryland Baltimore County
1000 Hilltop Circle
Baltimore, MD, 21250
Office: ITE 319 Office Hours: TBD
Phone: 410-455-3549
** Meeting Time ** TuThu 2:30-3:45 Email: robucci@umbc.edu
Department of Computer Science and Electrical Engineering
University of Maryland Baltimore County
1000 Hilltop Circle
Baltimore, MD, 21250
Office: ITE 319 Office Hours: TBD
Phone: 410-455-3549
** Teaching Assistants and Graders ** : none
**Syllabus** : PDF
Calendar
| Date | Event / Lecture Material | Reading and Reference Material |
|------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-------------------------------------------|
| Aug 29 | **Lecture** 1 https://eclipse.umbc.edu/robucci/cmpeRSD/lectures/L01__DigitalSystemsDesign/L01__DigitalSystemsDesign.html | -- |
| Sept 2 (delayed) | **Lecture** 2 https://eclipse.umbc.edu/robucci/cmpeRSD/lectures/L02__Verilog/L02__Verilog.html | -- |
| Sept 4 | **Lecture** 2 https://eclipse.umbc.edu/robucci/cmpeRSD/lectures/L02__Verilog/L02__Verilog.html | -- |
| {info} Sept 10 | HW 1 Assigned [link](./hw1_2025/index.html) |--|
| Sept 16 | **Lecture** 3 [Debugging and Montitoring](https://eclipse.umbc.edu/robucci/cmpe316/lectures/L07__Debugging_and_Monitoring_Statements/) | see sample in hw |
| Sept 16 | **Lecture** 4 (skipped, but kept for reference only, no implicit requirement) [Synthesis and Loops](./Lectures/L04__Synth_and_Loops/) | -- |
| Sept 16 | **Lecture** 5 [Data Flow Modeling](./Lectures/Lecture05__Ch2_DataFlowModeling/) | Chapter 2 |
| {danger} Sept 17 | HW 1 Due |--|
| {info} Sept 18 | HW 2 Assigned [link](./hw/hw2_2025/hw2.html) |--|
| Sept 18 | **Lecture** 6 [Transformations](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture06__Transformations/) | Chapter 3 (3.2 only) |
| Sept 23 | **Lecture** 7 [Implementation](https://eclipse.umbc.edu/robucci/cmpeRSD/lectures/L07__Ch3_Ch4_Implementation/L07__Ch3_Ch4_Implementation.html) starting from HW Implementation | Chapter 4 |
| Sept 25 | **Lecture** 8 old [FSMD](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/L08__FSMD/) | Chapter 5 |
| Sept 25 | **Lecture** 8 [FSM_I](https://eclipse.umbc.edu/robucci/cmpeRSD/lectures/FSM_I/FSM_I.html) | Chapter 5 |
| Sept 25 | **Lecture** 8 [FSM_II](https://eclipse.umbc.edu/robucci/cmpeRSD/lectures/FSM_II/FSM_II.html) | Chapter 5 |
| {danger} Sept 25 | HW 2 Due |--|
| {info} Sept 26 | HW 3 Assigned [link](./hw/hw3_2025/hw3.html) |--|
| Sept 30 | **Lecture** 9 [Datapath I](https://eclipse.umbc.edu/robucci/cmpeRSD/lectures/Datapath_I/Datapath_I.html) | |
| Oct 2 | **Lecture** 10 Datapath 2 | |
| {danger} Oct 3 | HW 3 Due |--|
| {danger} Oct 7 | Exam 1 |--|
| {info} Sept 10 | HW 4 Assigned [link](./hw/hw4_2025/hw4.html) |--|
| Oct 6 | **Lecture** [Microprogrammed Architectures ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture09__Ch6_Microprogrammed_Architectures/) | Chapter 6 |
| {danger} Oct 17 | HW 4 Due |--|
| Oct 28 | **Lecture** [Timing Analysis ](https://eclipse.umbc.edu/robucci/cmpeRSD/lectures/Physical_Design_Flow_and_Timing_Analysis/)
**Applet** [Timing Violations Applet](https://covail.cs.umbc.edu/robucci/applets/timing_violations/)
https://covail.cs.umbc.edu/robucci/applets/metastable_violations
https://covail.cs.umbc.edu/robucci/applets/slack | Timing Analysis Concepts https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture14.pdf#page=10 Page 10-31 | | Oct 30 | **Lecture** 11 [Metastability ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture11__Metastability/) | Chapter 8 Book Chapter: https://drive.google.com/file/d/0B5MWE1meYfDbc0RHQmh4LUVnMVlSSmFqRlZnVFg3NXd1bG9j/view |
Previous **Applet** [Timing Violations Applet](https://covail.cs.umbc.edu/robucci/applets/timing_violations/)
https://covail.cs.umbc.edu/robucci/applets/metastable_violations
https://covail.cs.umbc.edu/robucci/applets/slack | Timing Analysis Concepts https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture14.pdf#page=10 Page 10-31 | | Oct 30 | **Lecture** 11 [Metastability ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture11__Metastability/) | Chapter 8 Book Chapter: https://drive.google.com/file/d/0B5MWE1meYfDbc0RHQmh4LUVnMVlSSmFqRlZnVFg3NXd1bG9j/view |
| Date | Event / Lecture Material | Reading and Reference Material |
|------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-------------------------------------------|
| Aug 31 | **Lecture** 1 Course introduction and [Codesign](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture01__Codesign/) | -- |
| Sept 2 | **Lecture** 2 [Events Timing and Testbenches](Lecture02__Events_Timing_and_Testbenches/L02__Events_Timing_and_Testbenches.html) old: https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture02__Events_Timing_and_Testbenches/) | -- |
| Sept 2 | [**Discussion** 1](./discussions/discussion01) | [**paper** Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!](http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf)
[**pratice** HW2](https://eclipse.umbc.edu/robucci/cmpe415/attachments/HW2.pdf) | | - | Debugging and Monitoring: https://eclipse.umbc.edu/robucci/cmpe316/lectures/L07__Debugging_and_Monitoring_Statements/ | - | Metalogic: https://eclipse.umbc.edu/robucci/cmpe316/lectures/L05__VerilogIntroIII/#metalogic-values| - | | - | Full and Parallel Case: https://eclipse.umbc.edu/robucci/cmpe316/lectures/L08__Full_and_Parallel_Case/| - | | Sept 8 | **Lecture** 2 - Verilog Stratefied Event Queue and Time Modeling [Events Timing and Testbenches](./Lectures/Lecture02__Events_Timing_and_Testbenches/) | [**paper** Correct Methods for Adding Delays to Verilog Behavioral Models !](http://www.sunburst-design.com/papers/CummingsHDLCON1999_BehavioralDelays_Rev1_1.pdf) | | Sept 8 | [**Discussion** 2](./discussions/discussion02) | [**paper** "full_case parallel_case", the Evil Twins of Verilog Synthesis](http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf)
[**slides** Full and Parallel Case](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture07__Full_and_Parallel.pdf) | | Sept 10,14 | **Lecture** 3 [Debugging and Monitoring](./Lectures/Lecture03__Debugging_and_Monitoring_Statements/)
**Lecture** 4 [Synthesis and Loops](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/L04__Synth_and_Loops/) | -- | | Sept 14 | [**Discussion** 3](./discussions/discussion03) | Preparation Reading:[**paper** Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill](http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf)
[**slides** Suggested Coding and Design](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture08__Suggesting_Coding_and_Design_Practices.pdf)
[**slides** Operators Operands Variables and Literals](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture09__Operators_Operands_Variables_Literals.pdf) | | Sept | **Lecture** 4 [Synthesis and Loops](./Lectures/L04__Synth_and_Loops/) | - | | Sept 16 | **Lecture** 5 [Data Flow Modeling](./Lectures/Lecture05__Ch2_DataFlowModeling/) | Chapter 2 | | Sept 21 | **Lecture** 6 [Transformations](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture06__Transformations/) | Chapter 3 | | Sept 21 | [**Discussion** 4](./discussions/discussion04) | [**paper** The Fundamentals of Efficient Synthesizable Finite State MachineDesign using NC-Verilog and BuildGates](http://www.sunburst-design.com/papers/CummingsICU2002_FSMFundamentals.pdf) | Sept 24,Sept 29 | **Lecture** 7 [Implementation](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/L07__Ch3_Ch4_Implementation/ ) | Chapter 4 | | Sept 29, Oct 1 | **Lecture** 8 [FSMD ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/L08__FSMD/) | Chapter 5 | | Sept 29 | [**Discussion** 5](./discussions/discussion05) | [IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language - Redline](https://ieeexplore.ieee.org/document/5985443)
[**paper** SystemVerilogFSM](http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf) | | Oct 6 | **Lecture** 9 [Microprogrammed Architectures ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture09__Ch6_Microprogrammed_Architectures/) | Chapter 6 | | Oct 6 | [**Discussion** 6](./discussions/discussion06) | | -- | | Oct 8,13 | **Lecture** 10 [General-Purpose Embedded Cores ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture10__General-Purpose_Embedded_Cores/) | Chapter 7
OS Example: https://drive.google.com/file/d/0B5MWE1meYfDbNlFOZ3hYX3BxMUE/view | | Oct 13 | [**Discussion** 7](./discussions/discussion07) | | -- | | Oct 15 | **Lecture** 11 [Metastability ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture11__Metastability/) | Chapter 8 Book Chapter: https://drive.google.com/file/d/0B5MWE1meYfDbc0RHQmh4LUVnMVlSSmFqRlZnVFg3NXd1bG9j/view | | Oct 20 | **Lecture** 12 [Managing Metastability ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture12__ManagingMetaStability/) | -- | | Oct 22 | **Lecture** 13 [Timing Analysis ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture13__TimingAnalysis/)
**Applet** [Timing Violations Applet](https://covail.cs.umbc.edu/robucci/applets/timing_violations/) | Timing Analysis Concepts https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture14.pdf#page=10 Page 10-31 | | Oct 27
(delayed from Oct 20) | [**Discussion** 8](./discussions/discussion08) | -- | | | **Lecture** 14 [MultiClock-Domain Design Techniques Guided Paper Review with Lecture Notes ](https://drive.google.com/file/d/1DTfBRWXQ4PWybatG9NUcY0AAxbkJJzbZ/view) | [Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs (2001)](http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk.pdf) Details of Code for FIFO implementation shown at end of 2002 paper: [Simulation and Synthesis Techniques for Asynchronous FIFO Design (2002)](http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf) https://www.glassdoor.com/Interview/uk-digital-design-engineer-interview-questions-SRCH_IL.0,2_IN2_KO3,26.htm "Cisco Question" ; Apple Interview Question: https://www.glassdoor.com/Interview/Describe-how-a-multi-bit-synchronizer-async-fifo-handles-the-variable-delay-of-each-bit-QTN_1243086.htm | | | **Lecture** 15 [Communications and Clock Management ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture15__Communications_and_Clock_Management/) | [PLL and DLL Reading Material](https://drive.google.com/file/d/0B5MWE1meYfDbWUs1Tkl3QTh4YVhpNkJ6ZVhFOGJEZERMeFV3/view?usp=sharing) | | Nov 2 | **Dicussion 9** [FIFO and PLL](./discussions/discussion09/) | | -- | | | **Lecture** 16 [Arithmetic and Signed Integer Part I ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture16__Signed_Integers_and_Arithmetic__PartI/) | -- | | Nov 8 | **Lecture** 16 [Arithmetic and Signed Integer Part II ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture16__Signed_Integers_and_Arithmetic__PartII/) | -- | | Nov 10 | **Lecture** 16 [Arithmetic and Signed Integer Part III ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture16__Signed_Integers_and_Arithmetic__PartIII/) | -- | | Nov 23 (finish) | **Leture** 17 [Data Path Blocks Intro ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture17__Datapath/) | -- | | | Additional Reference Material: [Data Path Blocks I ](https://drive.google.com/file/d/1h2tA38ZFAErG92Pc3pP8iGSkSnHvZkrf/view) | -- | | | Additional Reference Material: [Data Path Blocks II Multiply and Shift: ](https://drive.google.com/open?id=14gPqmR6q9yXXNyw7MxVUyLNXqiIwj3oo ) | -- | | Nov 23 | **Dicussion 10** [Advanced Custom Comonents](./discussions/discussion10/) | -- | | Dec 5 | Lecture 18/19 substitute https://docs.google.com/presentation/d/1f3UODqOjZ1SS6qChPdxcba0rRzfuSwGieE9NCm1NM-8/edit#slide=id.g31c588056d4_0_135 | -- | | Nov 30->Dec 10 | **Lecture** 18 [Iterative Implementation of Elementary Arithmetic Functions](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture18__Iterative_Implementations_of_Elementary_Arithmetic_Functions) | -- | | Dec 10 | **Lecture** 19 [Implementation of Elementary Functions](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture19__Implementation_of_Elementary_Functions/) | -- | | Dec 10 | **Lecture** 20 [CORDIC](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture20__CORDIC/) | CORDIC Ref. Design https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an263.pdf , https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/stx_cookbook.pdf Review Ch 2 | | | Additional Material: RAM and Interfaces | RAM User Guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ram.pdf
[**pratice** HW2](https://eclipse.umbc.edu/robucci/cmpe415/attachments/HW2.pdf) | | - | Debugging and Monitoring: https://eclipse.umbc.edu/robucci/cmpe316/lectures/L07__Debugging_and_Monitoring_Statements/ | - | Metalogic: https://eclipse.umbc.edu/robucci/cmpe316/lectures/L05__VerilogIntroIII/#metalogic-values| - | | - | Full and Parallel Case: https://eclipse.umbc.edu/robucci/cmpe316/lectures/L08__Full_and_Parallel_Case/| - | | Sept 8 | **Lecture** 2 - Verilog Stratefied Event Queue and Time Modeling [Events Timing and Testbenches](./Lectures/Lecture02__Events_Timing_and_Testbenches/) | [**paper** Correct Methods for Adding Delays to Verilog Behavioral Models !](http://www.sunburst-design.com/papers/CummingsHDLCON1999_BehavioralDelays_Rev1_1.pdf) | | Sept 8 | [**Discussion** 2](./discussions/discussion02) | [**paper** "full_case parallel_case", the Evil Twins of Verilog Synthesis](http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf)
[**slides** Full and Parallel Case](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture07__Full_and_Parallel.pdf) | | Sept 10,14 | **Lecture** 3 [Debugging and Monitoring](./Lectures/Lecture03__Debugging_and_Monitoring_Statements/)
**Lecture** 4 [Synthesis and Loops](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/L04__Synth_and_Loops/) | -- | | Sept 14 | [**Discussion** 3](./discussions/discussion03) | Preparation Reading:[**paper** Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill](http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf)
[**slides** Suggested Coding and Design](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture08__Suggesting_Coding_and_Design_Practices.pdf)
[**slides** Operators Operands Variables and Literals](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture09__Operators_Operands_Variables_Literals.pdf) | | Sept | **Lecture** 4 [Synthesis and Loops](./Lectures/L04__Synth_and_Loops/) | - | | Sept 16 | **Lecture** 5 [Data Flow Modeling](./Lectures/Lecture05__Ch2_DataFlowModeling/) | Chapter 2 | | Sept 21 | **Lecture** 6 [Transformations](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture06__Transformations/) | Chapter 3 | | Sept 21 | [**Discussion** 4](./discussions/discussion04) | [**paper** The Fundamentals of Efficient Synthesizable Finite State MachineDesign using NC-Verilog and BuildGates](http://www.sunburst-design.com/papers/CummingsICU2002_FSMFundamentals.pdf) | Sept 24,Sept 29 | **Lecture** 7 [Implementation](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/L07__Ch3_Ch4_Implementation/ ) | Chapter 4 | | Sept 29, Oct 1 | **Lecture** 8 [FSMD ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/L08__FSMD/) | Chapter 5 | | Sept 29 | [**Discussion** 5](./discussions/discussion05) | [IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language - Redline](https://ieeexplore.ieee.org/document/5985443)
[**paper** SystemVerilogFSM](http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf) | | Oct 6 | **Lecture** 9 [Microprogrammed Architectures ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture09__Ch6_Microprogrammed_Architectures/) | Chapter 6 | | Oct 6 | [**Discussion** 6](./discussions/discussion06) | | -- | | Oct 8,13 | **Lecture** 10 [General-Purpose Embedded Cores ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture10__General-Purpose_Embedded_Cores/) | Chapter 7
OS Example: https://drive.google.com/file/d/0B5MWE1meYfDbNlFOZ3hYX3BxMUE/view | | Oct 13 | [**Discussion** 7](./discussions/discussion07) | | -- | | Oct 15 | **Lecture** 11 [Metastability ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture11__Metastability/) | Chapter 8 Book Chapter: https://drive.google.com/file/d/0B5MWE1meYfDbc0RHQmh4LUVnMVlSSmFqRlZnVFg3NXd1bG9j/view | | Oct 20 | **Lecture** 12 [Managing Metastability ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture12__ManagingMetaStability/) | -- | | Oct 22 | **Lecture** 13 [Timing Analysis ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture13__TimingAnalysis/)
**Applet** [Timing Violations Applet](https://covail.cs.umbc.edu/robucci/applets/timing_violations/) | Timing Analysis Concepts https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture14.pdf#page=10 Page 10-31 | | Oct 27
(delayed from Oct 20) | [**Discussion** 8](./discussions/discussion08) | -- | | | **Lecture** 14 [MultiClock-Domain Design Techniques Guided Paper Review with Lecture Notes ](https://drive.google.com/file/d/1DTfBRWXQ4PWybatG9NUcY0AAxbkJJzbZ/view) | [Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs (2001)](http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk.pdf) Details of Code for FIFO implementation shown at end of 2002 paper: [Simulation and Synthesis Techniques for Asynchronous FIFO Design (2002)](http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf) https://www.glassdoor.com/Interview/uk-digital-design-engineer-interview-questions-SRCH_IL.0,2_IN2_KO3,26.htm "Cisco Question" ; Apple Interview Question: https://www.glassdoor.com/Interview/Describe-how-a-multi-bit-synchronizer-async-fifo-handles-the-variable-delay-of-each-bit-QTN_1243086.htm | | | **Lecture** 15 [Communications and Clock Management ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture15__Communications_and_Clock_Management/) | [PLL and DLL Reading Material](https://drive.google.com/file/d/0B5MWE1meYfDbWUs1Tkl3QTh4YVhpNkJ6ZVhFOGJEZERMeFV3/view?usp=sharing) | | Nov 2 | **Dicussion 9** [FIFO and PLL](./discussions/discussion09/) | | -- | | | **Lecture** 16 [Arithmetic and Signed Integer Part I ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture16__Signed_Integers_and_Arithmetic__PartI/) | -- | | Nov 8 | **Lecture** 16 [Arithmetic and Signed Integer Part II ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture16__Signed_Integers_and_Arithmetic__PartII/) | -- | | Nov 10 | **Lecture** 16 [Arithmetic and Signed Integer Part III ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture16__Signed_Integers_and_Arithmetic__PartIII/) | -- | | Nov 23 (finish) | **Leture** 17 [Data Path Blocks Intro ](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture17__Datapath/) | -- | | | Additional Reference Material: [Data Path Blocks I ](https://drive.google.com/file/d/1h2tA38ZFAErG92Pc3pP8iGSkSnHvZkrf/view) | -- | | | Additional Reference Material: [Data Path Blocks II Multiply and Shift: ](https://drive.google.com/open?id=14gPqmR6q9yXXNyw7MxVUyLNXqiIwj3oo ) | -- | | Nov 23 | **Dicussion 10** [Advanced Custom Comonents](./discussions/discussion10/) | -- | | Dec 5 | Lecture 18/19 substitute https://docs.google.com/presentation/d/1f3UODqOjZ1SS6qChPdxcba0rRzfuSwGieE9NCm1NM-8/edit#slide=id.g31c588056d4_0_135 | -- | | Nov 30->Dec 10 | **Lecture** 18 [Iterative Implementation of Elementary Arithmetic Functions](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture18__Iterative_Implementations_of_Elementary_Arithmetic_Functions) | -- | | Dec 10 | **Lecture** 19 [Implementation of Elementary Functions](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture19__Implementation_of_Elementary_Functions/) | -- | | Dec 10 | **Lecture** 20 [CORDIC](https://eclipse.umbc.edu/robucci/cmpeRSD/Lectures/Lecture20__CORDIC/) | CORDIC Ref. Design https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an263.pdf , https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/stx_cookbook.pdf Review Ch 2 | | | Additional Material: RAM and Interfaces | RAM User Guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ram.pdf
| Date | Event / Lecture Material | Reading and Reference Material
|------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------|-------------------------------------------
| | [Codesign ](./Lectures/Lecture01__Codesign/) | -- |
| Sept 10 | Lecture - Verilog Stratefied Event Queue and Time Modeling [Events Timing and Testbenches](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture05__Events_Timing_Testbeches.pdf) [Debugging and Monitoring](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture06__Debugging_and_Monitoring_Statements.pdf) | http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf |
| | [Synthesis and Loops](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture10__Synth_and_Loops.pdf) | -- |
| | [Data Flow Modeling](./Lectures/Lecture02__Ch2_DataFlowModeling/) | -- |
| | [Transformations](./Lectures/Lecture03__Transformations/) | -- |
| | [Implementation ](./Lectures/Lecture04__Ch3_Ch4_Implementation/ ) | -- |
| | [FSMD ](./Lectures/Lecture05__FSMD/) | -- |
| | [Microprogrammed Architectures ](./Lectures/Lecture06__Ch6_Microprogrammed_Architectures/) | -- |
| | [General-Purpose Embedded Cores ](./Lectures/Lecture07__General-Purpose_Embedded_Cores/) | OS Example: https://drive.google.com/file/d/0B5MWE1meYfDbNlFOZ3hYX3BxMUE/view |
| | [Metastability ](./Lectures/Lecture08__Metastability/) | Book Chapter: https://drive.google.com/file/d/0B5MWE1meYfDbc0RHQmh4LUVnMVlSSmFqRlZnVFg3NXd1bG9j/view |
| | [Managing Metastability ](./Lectures/Lecture09__ManagingMetaStability/) | -- |
| | [Timing Analysis ](./Lectures/Lecture10__TimingAnalysis/) | Timing Analysis Concepts https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture14.pdf#page=10 Page 10-31 |
| | [MultiClock-Domain Design Techniques ](./Lectures/Lecture11__MultiClockDomainDesign/) | [Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs (2001)](http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk.pdf) Details of Code for FIFO implementation shown at end of 2002 paper: [Simulation and Synthesis Techniques for Asynchronous FIFO Design (2002)](http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf) https://www.glassdoor.com/Interview/uk-digital-design-engineer-interview-questions-SRCH_IL.0,2_IN2_KO3,26.htm "Cisco Question" ; Apple Interview Question: https://www.glassdoor.com/Interview/Describe-how-a-multi-bit-synchronizer-async-fifo-handles-the-variable-delay-of-each-bit-QTN_1243086.htm |
| | [Communications and Clock Management ](./Lectures/Lecture12__Communications_and_Clock_Management/) | -- |
| | [Arithmetic and Signed Integer ](./Lectures/Lecture13__Signed_Integers_and_Arithmetic/) | -- |
| | [Data Path Blocks Intro ](./Lectures/Lecture14__Datapath/) | -- |
| | [Data Path Blocks I ](https://drive.google.com/file/d/1h2tA38ZFAErG92Pc3pP8iGSkSnHvZkrf/view) | -- |
| | [Data Path Blocks II Multiply and Shift: ](https://drive.google.com/open?id=14gPqmR6q9yXXNyw7MxVUyLNXqiIwj3oo ) | -- |
| | [Iterative Implementation of Elementary Arithmetic Functions](./Lectures/Lecture16__Iterative_Implementations_of_Elementary_Arithmetic_Functions) | -- |
| | [Implementation of Elementary Functions](./Lectures/Lecture17__Implementation_of_Elementary_Functions/) | -- |
| | [CORDIC](./Lectures/Lecture18__CORDIC/) | CORDIC Ref. Design https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an263.pdf , https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/stx_cookbook.pdf Review Ch 2 |
| | RAM and Interfaces | RAM User Guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ram.pdf
Discussion
| Discussion | Materials |
|------------ | -- |
| Session 1 Intro to Verilog | [Discussion 1 Document](./discussions/discussion01/) |
| | CMPE415 HW2 Practice Questions: https://eclipse.umbc.edu/robucci/cmpe415/attachments/HW2.pdf |
| | Many Practice Questions: https://eclipse.umbc.edu/robucci/cmpe415/verilog_practice/index.html |
| Session 2 | [Discussion 2 Document](./discussions/discussion02/) |
| Session 3 | [Discussion 3 Document](./discussions/discussion03/) |
| | Preparation Reading: http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf |
| | [Slides Suggested Coding and Design](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture08__Suggesting_Coding_and_Design_Practices.pdf)|
| | [Slides Operators Operands Variables and Literals](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture09__Operators_Operands_Variables_Literals.pdf)|
| Session 4 | [Discussion 4 Document](./discussions/discussion04/) |
| | Preparation Reading: FSM Papers in References Below|
| | [Slides FSM I](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture11__FSM_I.pdf) (1/2 hour)|
| | [The Fundamentals of Efficient Synthesizable Finite State MachineDesign using NC-Verilog and BuildGates](http://www.sunburst-design.com/papers/CummingsICU2002_FSMFundamentals.pdf)
| | [User Guide for Board](https://www.intel.com/content/dam/altera-www/global/en_US/portal/dsn/42/doc-us-dsnbk-42-1004282204-de1-soc-user-manual.pdf)
| Session 5 | [Discussion 5 Document System Verilog and Embedded Processors](./discussions/discussion05/) |
| | [Introduction to SystemVerilog](./discussions/discussion05_systemverilog/) emphasis on features for state machines |
| | [Introduction to Use of Embedded Processors, Nios II](discussions/discussion05_niosii/) (2 hours) |
| | [IntroToNiosIIProcessor](https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/nios2/n2cpu_nii51001.pdf) PDF PAGE 3 Figure 1-1 Example of a NiosII Processor System |
| Session 6 | [Setting Up SD Card and Linux Terminal](./discussions/discussion06/discussion06.html) |
| Session 7 | [Custom Component and UBOOT](./discussions/discussion07/) |
| Session 8 | [Embedded Code Developement](./discussions/discussion08/) |
| Session 9 | [FIFO and PLL](./discussions/discussion09/) |
| Session 10 | [Advanced Custom Comonents](./discussions/discussion10/) |
Assignments and Projects
| Assignment | Link |
|------------ | -- |
| {info} 2025 HW 1 | [link](./hw1_2025/index.html) |
| {info} 2025 HW 2 | [link](./hw/hw2_2025/hw2.html) |
| Assignment | Link |
|------------ | -- |
| 2024 HW1 | https://eclipse.umbc.edu/robucci/cmpeRSD/hw/hw1/hw1.html |
| 2024 HW2 | https://eclipse.umbc.edu/robucci/cmpeRSD/hw/hw2/hw2.html |
| 2024 HW3 | https://eclipse.umbc.edu/robucci/cmpeRSD/hw/hw3/hw3.html |
| 2024 HW4 | https://eclipse.umbc.edu/robucci/cmpeRSD/hw/hw4/hw4.html |
| 2024 HW5 | https://docs.google.com/document/d/1aloxS9zaHIMTcoyS07xwW0lcT0dC0HiTHbfVNjlYQm0/edit?tab=t.0#heading=h.p1px6uxc9xpp previous year: https://eclipse.umbc.edu/robucci/cmpeRSD/hw/hw5/hw5.html |
| 2024 HW6 | https://docs.google.com/document/d/10lp6ITHeSYK-7yGnHB-Wa87NZD89ppi6pf_5sY_qUWY/edit?tab=t.0#heading=h.upndongvb4lr previous year: https://eclipse.umbc.edu/robucci/cmpeRSD/hw/hw6/hw6.html |
| 2024 HW7 | https://docs.google.com/document/d/1F7h8eEoI3hSV386etG21GP8GwgI5mIPwsHSEfVUkM40/edit?tab=t.0#heading=h.bli9qwy3sdm3 previous year: https://eclipse.umbc.edu/robucci/cmpeRSD/hw/hw7/hw7.html |
| 2024 HW8 | https://docs.google.com/document/d/1mLDGI-0gZwUSdj5lnVbXC2ASVzDRHI-sUvel41wyK3s/edit?tab=t.0 previous year: https://eclipse.umbc.edu/robucci/cmpeRSD/hw/hw8/hw8.html |
**Course Project**: [Project](./project/project.html)
2018 Assignments and Project
| Assignment | Link |
| ---------- | ---- |
| HW1 | https://drive.google.com/file/d/17ifjbEhgE6ZYjf_sglbc5MsQCjiIU34a/view |
| HW2 | https://drive.google.com/file/d/1VAKkwyBXP65PQB8m3NdVyOHxnuCi25hx/view |
| HW3 | https://drive.google.com/file/d/16sp7SNwbdrMFwL-QXS5f9hYpTS2gtM2U/view , [HW3_cordic.c](https://drive.google.com/file/d/1Y0_RlVwRK1s2uEDSCZ_DAVxYatAzhmMP/view) |
**Course Project**: https://docs.google.com/document/d/1kHsDqM-oH8kx_zP9FMAfC-bOpVjzHQvAuKggnAnwRRI/view
Reading and References
* Patrick R. Schaumont, A Practical Introduction to Hardware/Software Codesign 2nd Edition, Springer (ISBN:978-1461437369)
* [1364-2005 - IEEE Standard for Verilog Hardware Description Language](http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1620870) available from UMBC
* Digital Design (Verilog): An Embedded Systems Approach Using Verilog, Peter J. Ashenden (Author) ISBN-13:9780123695277 Amazon
* The Design Warrior’s Guide to FPGAs, Devices, Tools and Flows, Clive Maxfield (Author) ISBN-13: 978-0750676045 Amazon
* [ASIC World Verilog](http://www.asic-world.com/verilog/index.html) by Deepak Kumar Tala (HDL Design/Coding Styles
* [Verilog HDL Quick Reference Guide](http://www.sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf) based on the Verilog-2001 Standard by Stuart Sutherland (http://www.sutherland-hdl.com/books_and_guides.html#V2K HDL Ref)
* The Verilog® Hardware Description Language, Donald E. Thomas (Author), Philip R. Moorby (Author) ISBN:9781402070891 Amazon
* Modeling, Synthesis, and Rapid Prototyping with the VERILOG (TM) HDL, Michael D. Ciletti (Author) ISBN-13:9780139773983 Amazon
* [Verilog Papers by Cliff Cummings of Sunburst Design, Inc.](http://www.sunburst-design.com/papers/#papers_top )
### Undergraduate Course
* Verilog Slides: https://eclipse.umbc.edu/robucci/cmpe415
### Quartus
Intel Quartus Prime and Pro User Guide: https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/user-guides.html
### Intel FPGA:
High-Performance ALM and Interconnect: https://www.intel.com/content/www/us/en/programmable/products/fpga/features/stx-architecture.html
### Design and Coding
* [Intel Quartus Prime Pro Edition User Guide: Design Recommendations](https://www.intel.com/content/altera-www/global/en_us/index/documentation/sbc1513987577203.html)
* [Recommended HDL Coding Styles](https://www.intel.com/content/altera-www/global/en_us/index/documentation/sbc1513987577203.html#mwh1409959570946)
* [Recommended Design Practices]( https://www.intel.com/content/altera-www/global/en_us/index/documentation/sbc1513987577203.html#mwh1409959483992)
* [Managing Metastability with the Intel Quartus Prime Software](https://www.intel.com/content/altera-www/global/en_us/index/documentation/sbc1513987577203.html#mwh1409959644819)
### Full and Parallel Case
* https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture03_Full_and_Parallel.pdf
emphasis on proper implementation combinatorial logic truth tables through of “decision tree” type descriptions. This is a building block whose mastery should precede description of complex concurrent execution and complex state machines in HDL.
* http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf
### Verilog Execution Model and Event Queue
* See Slides in https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture05_Events_Timing_Testbeches.pdf
* Understand monitor queue, non-blocking vs blocking, use of $strobe/$monitor for “non-blocking” vs $display
* regarding the Verilog execution model and event queue:
* Section 11 pg 158-162 of http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1620780
* http://insights.sigasi.com/opinion/jan/vhdls-crown-jewel.html
* http://www.vlsiinterviewquestions.org/2012/07/18/verilog-execution-order/
* VHDL vs Verilog
* In VHDL, variables update immediately upon assignment and do not facilitate communication between processes. Signals are used to communicate between processes and are updated at the end of a simulation cycle.
* In Verilog, we have to adopt a coding convention that mimics these.
### Coding Practices
* Suggested Coding and Design Practices: https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture08__Suggesting_Coding_and_Design_Practices.pdf Particularly ~slide 3: Suggested Procedural RTL Coding Practices
* http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf
### Verilog Timing and Testbenches:
* https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture05_Events_Timing_Testbeches.pdf
### FSM and FSMD
* Related Course Text Readings
* Ch5 and Ch6 of 2nd Ed (Ch4&Ch5 of 1st ed)
* FSM(D) Verilog Slides
* https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture11__FSM_I.pdf
* https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture12__FSM_II.pdf
* From http://www.sunburst-design.com/papers/
* http://www.sunburst-design.com/papers/CummingsSNUG1998SJ_FSM.pdf
* http://www.sunburst-design.com/papers/CummingsICU2002_FSMFundamentals.pdf
* http://www.sunburst-design.com/papers/CummingsSNUG2004Boston_2StateSims.pdf
* System Verilog : http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf Section 10. and 11. Starting on page 29 of 53 discuss in class