CMPE 691

• Verilog Slides: https://eclipse.umbc.edu/robucci/cmpe415

Intel Quartus Prime and Pro User Guide: https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/user-guides.html

High-Performance ALM and Interconnect: https://www.intel.com/content/www/us/en/programmable/products/fpga/features/stx-architecture.html

• Intel Quartus Prime Pro Edition User Guide: Design Recommendations
  • Recommended HDL Coding Styles
  • Recommended Design Practices
  • Managing Metastability with the Intel Quartus Prime Software

• https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture03_Full_and_Parallel.pdf emphasis on proper implementation combinatorial logic truth tables through of “decision tree” type descriptions. This is a building block whose mastery should precede description of complex concurrent execution and complex state machines in HDL.
• http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf

• See Slides in https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture05_Events_Timing_Testbeches.pdf
  • Understand monitor queue, non-blocking vs blocking, use of $strobe/$monitor for “non-blocking” vs $display
• regarding the Verilog execution model and event queue:
  • Section 11 pg 158-162 of http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1620780
  • http://insights.sigasi.com/opinion/jan/vhdls-crown-jewel.html
  • http://www.vlsiinterviewquestions.org/2012/07/18/verilog-execution-order/
  • VHDL vs Verilog
    • In VHDL, variables update immediately upon assignment and do not facilitate communication between processes. Signals are used to communicate between processes and are updated at the end of a simulation cycle.
    • In Verilog, we have to adopt a coding convention that mimics these.

• Suggested Coding and Design Practices: https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture08__Suggesting_Coding_and_Design_Practices.pdf Particularly ~slide 3: Suggested Procedural RTL Coding Practices
• http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf

• https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture05_Events_Timing_Testbeches.pdf

• Related Course Text Readings
  • Ch5 and Ch6 of 2nd Ed (Ch4&Ch5 of 1st ed)
• FSM(D) Verilog Slides
  • https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture11__FSM_I.pdf
  • https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture12__FSM_II.pdf
• From http://www.sunburst-design.com/papers/
  • http://www.sunburst-design.com/papers/CummingsSNUG1998SJ_FSM.pdf
  • http://www.sunburst-design.com/papers/CummingsICU2002_FSMFundamentals.pdf
  • http://www.sunburst-design.com/papers/CummingsSNUG2004Boston_2StateSims.pdf
  • System Verilog : http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf Section 10. and 11. Starting on page 29 of 53 discuss in class

For assignments you can use some CSEE Linux servers or the ITE 375 lab Linux computers

• ssh <username>@cadence1.cs.umbc.edu
• ssh <username>@cadence2.cs.umbc.edu
• ssh <username>@ite375pc04@cs.umbc.edu
• ssh <username>@ite375pc05@cs.umbc.edu
• ssh <username>@ite375pc06@cs.umbc.edu
• …

Instructions that I provide are based on the assumption that you are using a bash shell.

once you login, check your shell using the following command

echo $SHELL

if it the answer is not bash, simply run the bash command to enter a bash shell

bash

one of the tools to use is Cadence Xcelium Logic Simulator

it is available through this command:

/umbc/software/scripts/launch_cadence_xrun.sh

for convenience you may setup a "shortcut" as xrun and specify the path to it in your default login scripts

mkdir -p ~/bin
ln -s /umbc/software/scripts/launch_cadence_xrun.sh ~/bin/xrun
echo 'export PATH=~/bin${PATH:+:${PATH}}' >> ~/.bashrc

this will be picked up the next time you enter a bash shell

create a file hello.sv with the following contents

module test;
   initial begin
      $display("**hello world**");
   end
endmodule

various tools used in the course will create work/build subdirectories and temporary files. You should work from new clean and organized directories when running the tools

/umbc/software/scripts/launch_cadence_xrun.sh hello.sv

or

xrun hello.sv

Expected Results:

TOOL:    xrun(64)    23.09-s013: Started on Sep 05, 2025 at 10:51:29 EDT
xrun(64): 23.09-s013: (c) Copyright 1995-2024 Cadence Design Systems, Inc.
file: /tmp/babel-xElt4C/neIB6l4.sv
    module worklib.test:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        test
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.test:sv <0x167d8345>
            streams:   1, words:   464
    Building instance specific data structures.
    Loading native compiled code:     .................... Done
    Design hierarchy summary:
                 Instances  Unique
        Modules:         1       1
        Initial blocks:  1       1
    Writing initial simulation snapshot: worklib.test:sv
Loading snapshot worklib.test:sv .................... Done
xcelium> source /umbc/software/cadence/installs/XCELIUM2309/tools/xcelium/files/xmsimrc
xcelium> run
**hello world**
xmsim: *W,RNQUIE: Simulation is complete.
xcelium> exit
TOOL:   xrun(64)    23.09-s013: Exiting on Sep 05, 2025 at 10:51:29 EDT  (total: 00:00:00)