**Course Title** : Reconfigurable System Design
**Course Number** : CMPE 691
**Credits**: 3.00
**Description**:
**Prequisite ** : Courses covering C, HDL, FPGA
**Instructor**
Dr. Ryan Robucci
Assistant Professor
Email: robucci@umbc.edu
Department of Computer Science and Electrical Engineering
University of Maryland Baltimore County
1000 Hilltop Circle
Baltimore, MD, 21250
Office: ITE 319 Office Hours: TBD
Phone: 410-455-3549
** Meeting Time ** TuThu 4:00-5:15 ** Teaching Assistants and Graders ** : * TA: Saad Rahman - umbc email: rahman2 **Syllabus** : PDF



Calendar

| Date | Event / Lecture Material | Reading and Reference Material |------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------|------------------------------------------- | | [Codesign ](./Lectures/Lecture01__Codesign/) | -- | | Sept 10 | Lecture - Verilog Stratefied Event Queue and Time Modeling [Events Timing and Testbenches](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture05__Events_Timing_Testbeches.pdf) [Debugging and Monitoring](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture06__Debugging_and_Monitoring_Statements.pdf) | -- | | | [Synthesis and Loops](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture10__Synth_and_Loops.pdf) | -- | | | [Data Flow Modeling](./Lectures/Lecture02__Ch2_DataFlowModeling/) | -- | | | [Transformations](./Lectures/Lecture03__Transformations/) | -- | | | [Implementation ](./Lectures/Lecture04__Ch3_Ch4_Implementation/ ) | -- | | | [FSMD ](./Lectures/Lecture05__FSMD/) | -- | | | [Microprogrammed Architectures ](./Lectures/Lecture06__Ch6_Microprogrammed_Architectures/) | -- | | | [General-Purpose Embedded Cores ](./Lectures/Lecture07__General-Purpose_Embedded_Cores/) | OS Example: https://drive.google.com/file/d/0B5MWE1meYfDbNlFOZ3hYX3BxMUE/view | | | [Metastability](./Lectures/Lecture08__Metastability/)| Book Chapter: https://drive.google.com/file/d/0B5MWE1meYfDbc0RHQmh4LUVnMVlSSmFqRlZnVFg3NXd1bG9j/view | | | [Managing Metastability](./Lectures/Lecture09__ManagingMetaStability/)| -- | | | [Timing Analysis](./Lectures/Lecture10__TimingAnalysis/) | Timing Analysis Concepts https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture14.pdf#page=10 Page 10-31 | | | [MultiClock-Domain Design Techniques](./Lectures/Lecture11__MultiClockDomainDesign/) | [Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs (2001)](http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk.pdf) Details of Code for FIFO implementation shown at end of 2002 paper: [Simulation and Synthesis Techniques for Asynchronous FIFO Design (2002)](http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf) https://www.glassdoor.com/Interview/uk-digital-design-engineer-interview-questions-SRCH_IL.0,2_IN2_KO3,26.htm "Cisco Question" ; Apple Interview Question: https://www.glassdoor.com/Interview/Describe-how-a-multi-bit-synchronizer-async-fifo-handles-the-variable-delay-of-each-bit-QTN_1243086.htm | | | [Communications and Clock Management ](./Lectures/Lecture12__Communications_and_Clock_Management/) | -- | | | [Arithmetic and Signed Integer ](./Lectures/Lecture13__Signed_Integers_and_Arithmetic/) | -- | | | [Data Path Blocks Intro ](./Lectures/Lecture14__Datapath/) | -- | | | [Data Path Blocks I ](https://drive.google.com/file/d/1h2tA38ZFAErG92Pc3pP8iGSkSnHvZkrf/view) | -- | | | [Data Path Blocks II Multiply and Shift: ](https://drive.google.com/open?id=14gPqmR6q9yXXNyw7MxVUyLNXqiIwj3oo ) | -- | | | [Iterative Implementation of Elementary Arithmetic Functions](./Lectures/Lecture16__Iterative_Implementations_of_Elementary_Arithmetic_Functions) | -- | | | [Implementation of Elementary Functions](./Lectures/Lecture17__Implementation_of_Elementary_Functions/) | -- | | | [CORDIC](./Lectures/Lecture18__CORDIC/) | CORDIC Ref. Design https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an263.pdf , https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/stx_cookbook.pdf Review Ch 2 | | | RAM and Interfaces | RAM User Guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ram.pdf

Discussion

| Discussion | Materials | |------------ | -- | | Session 1: Intro to Verilog | [Session 1 Document](./discussion/session1/index.html) | | | [IntroVerilogI](https://drive.google.com/open?id=15OCgYw8HKzOV_Ru7AHS2GsG9XNJonTlh) | | | [IntroVerilogII](https://drive.google.com/open?id=1oSnAgj7PkMWWFWNaDAYRJYcYLJ3yr7BS) | | | [IntroVerilogIII](https://drive.google.com/open?id=1SRypy6lNe6XbFC8iK8rapxC595mhuG_P) | | | CMPE415 HW2 Practice Questions: https://eclipse.umbc.edu/robucci/cmpe415/attachments/HW2.pdf | | | Many Practice Questions: https://eclipse.umbc.edu/robucci/cmpe415/verilog_practice/index.html | | Session 2: | [Session 2 Document](./discussion/session2/index.html) | | Session 3: | Preparation Reading: http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf| | | [Slides Suggested Coding and Design](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture08__Suggesting_Coding_and_Design_Practices.pdf)| | | [Slides Operators Operands Variables and Literals](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture09__Operators_Operands_Variables_Literals.pdf)| | Session 4: | Preparation Reading: FSM Papers in References Below| | | [Slides FSM I](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture11__FSM_I.pdf) (1/2 hour)| | | Verilog State Machine (timer.v and notes pending from TA) | | Session 5: | [Introduction to SystemVerilog](./discussion/session5/DiscussionSystemVerilog/) emphasis on features for state machines | | | [Introduction to Use of Embedded Processors](https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture03_FPGATechIII.pdf) PDF PAGES 6-12 | | [IntroToNiosIIProcessor](https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/nios2/n2cpu_nii51001.pdf) PDF PAGE 3 Figure 1-1 Example of a NiosII Processor System | | | TODO:post solution zip | | | [Tutorial on NIOS Processor](./discussion/session5/DiscussionNiosII/) (2 hours) | | Session 6: | NiosII I/O programming : Pending Document from TA | | Session 7: Part I | [Setting Up SD Card and Linux Terminal](./discussion/session7/linux_sdcard_terminal.html) | | Session 7: Part II | [Custom Component and UBOOT](./discussion/session7/custom_component_uboot/) | | Session 8: | [Embedded Code Developement](./discussion/session8/index.html) |

Assignments and Projects

| Assignment | Link | | ---------- | ---- | | HW1 | https://eclipse.umbc.edu/robucci/cmpeRSD/hw/hw1/index.html | | HW2 | https://eclipse.umbc.edu/robucci/cmpeRSD/hw/hw2/index.html | | HW3 | https://eclipse.umbc.edu/robucci/cmpeRSD/hw/hw3/index.html |
Previous

2018 Assignments and Project

| Assignment | Link | | ---------- | ---- | | HW1 | https://drive.google.com/file/d/17ifjbEhgE6ZYjf_sglbc5MsQCjiIU34a/view | | HW2 | https://drive.google.com/file/d/1VAKkwyBXP65PQB8m3NdVyOHxnuCi25hx/view | | HW3 | https://drive.google.com/file/d/16sp7SNwbdrMFwL-QXS5f9hYpTS2gtM2U/view , [HW3_cordic.c](https://drive.google.com/file/d/1Y0_RlVwRK1s2uEDSCZ_DAVxYatAzhmMP/view) | **Course Project**: https://docs.google.com/document/d/1kHsDqM-oH8kx_zP9FMAfC-bOpVjzHQvAuKggnAnwRRI/view

Reading and References

* Patrick R. Schaumont, A Practical Introduction to Hardware/Software Codesign 2nd Edition, Springer (ISBN:978-1461437369) * [1364-2005 - IEEE Standard for Verilog Hardware Description Language](http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1620870) available from UMBC * Digital Design (Verilog): An Embedded Systems Approach Using Verilog, Peter J. Ashenden (Author) ISBN-13:9780123695277 Amazon * The Design Warrior’s Guide to FPGAs, Devices, Tools and Flows, Clive Maxfield (Author) ISBN-13: 978-0750676045 Amazon * [ASIC World Verilog](http://www.asic-world.com/verilog/index.html) by Deepak Kumar Tala (HDL Design/Coding Styles * [Verilog HDL Quick Reference Guide](http://www.sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf) based on the Verilog-2001 Standard by Stuart Sutherland (http://www.sutherland-hdl.com/books_and_guides.html#V2K HDL Ref) * The Verilog® Hardware Description Language, Donald E. Thomas (Author), Philip R. Moorby (Author) ISBN:9781402070891 Amazon * Modeling, Synthesis, and Rapid Prototyping with the VERILOG (TM) HDL, Michael D. Ciletti (Author) ISBN-13:9780139773983 Amazon * [Verilog Papers by Cliff Cummings of Sunburst Design, Inc.](http://www.sunburst-design.com/papers/#papers_top )
### Undergraduate Course * Verilog Slides: https://eclipse.umbc.edu/robucci/cmpe415 ### Quartus Intel Quartus Prime and Pro User Guide: https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/user-guides.html ### Intel FPGA: High-Performance ALM and Interconnect: https://www.intel.com/content/www/us/en/programmable/products/fpga/features/stx-architecture.html ### Design and Coding * [Intel Quartus Prime Pro Edition User Guide: Design Recommendations](https://www.intel.com/content/altera-www/global/en_us/index/documentation/sbc1513987577203.html) * [Recommended HDL Coding Styles](https://www.intel.com/content/altera-www/global/en_us/index/documentation/sbc1513987577203.html#mwh1409959570946) * [Recommended Design Practices]( https://www.intel.com/content/altera-www/global/en_us/index/documentation/sbc1513987577203.html#mwh1409959483992) * [Managing Metastability with the Intel Quartus Prime Software](https://www.intel.com/content/altera-www/global/en_us/index/documentation/sbc1513987577203.html#mwh1409959644819) ### Full and Parallel Case * https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture03_Full_and_Parallel.pdf emphasis on proper implementation combinatorial logic truth tables through of “decision tree” type descriptions. This is a building block whose mastery should precede description of complex concurrent execution and complex state machines in HDL. * http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf ### Verilog Execution Model and Event Queue * See Slides in https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture05_Events_Timing_Testbeches.pdf * Understand monitor queue, non-blocking vs blocking, use of $strobe/$monitor for “non-blocking” vs $display * regarding the Verilog execution model and event queue: * Section 11 pg 158-162 of http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1620780 * http://insights.sigasi.com/opinion/jan/vhdls-crown-jewel.html * http://www.vlsiinterviewquestions.org/2012/07/18/verilog-execution-order/ * VHDL vs Verilog * In VHDL, variables update immediately upon assignment and do not facilitate communication between processes. Signals are used to communicate between processes and are updated at the end of a simulation cycle. * In Verilog, we have to adopt a coding convention that mimics these. ### Coding Practices * Suggested Coding and Design Practices: https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture08__Suggesting_Coding_and_Design_Practices.pdf Particularly ~slide 3: Suggested Procedural RTL Coding Practices * http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf ### Verilog Timing and Testbenches: * https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture05_Events_Timing_Testbeches.pdf ### FSM and FSMD * Related Course Text Readings * Ch5 and Ch6 of 2nd Ed (Ch4&Ch5 of 1st ed) * FSM(D) Verilog Slides * https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture11__FSM_I.pdf * https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture12__FSM_II.pdf * From http://www.sunburst-design.com/papers/ * http://www.sunburst-design.com/papers/CummingsSNUG1998SJ_FSM.pdf * http://www.sunburst-design.com/papers/CummingsICU2002_FSMFundamentals.pdf * http://www.sunburst-design.com/papers/CummingsSNUG2004Boston_2StateSims.pdf * System Verilog : http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf Section 10. and 11. Starting on page 29 of 53 discuss in class