Digital Abstraction and Noise

• consider a chain of digital gates
• signal corruption model: ideal gates with noise sources
• desire proper interpretation of binary values in presence of noise

Sources of Noise:

1. Electronic Thermal Noise
2. Power/Ground Current (through supply resistance)
3. Fast Signals in the System (large dI/dt induces drops in supply inductance)
4. Signal Coupling: Mutual Cap. and Mutual Inductive
5. Ringing (draw if required)
6. Temperature Differences between components affecting threshold voltages

(3-6 are esp. important for fast systems)

Additionally, manufacturing between devices can introduced fixed noise (e.g. offsets)

Noise Margins

• Noise margins ensure correct digital operation, maintaining the digital abstraction
• Require voltage constraints on inputs, and outputs to satisfiy input constraints for the downstream gate even in the presence of noise
• The difference between the output and input constraint are known as the Noise Margins

• Noise Margin High is the margin for '1'
• Noise Margin Low is the margin for '0'

Timing Requirements for Registers

• Registers tend to have voltage as well as specific timing requirements for the inputs
• Setup and Hold
  

• If violated, may get
  • Old Data
  • New Data
  • Metastable Output
    • Not conform to voltage specifications
    • May change in middle of clock period (multiple output transitions triggered by the clk)
      Possible Output transitions when expected is 0->1:
      

Metastabilty

Consider that an inverter represents contrain on allowed input, output ($V_1$,$V_2$) relationships:

Consider another inverter with the input and output connections reversed:

Consider a coupled set of inverters, setting constraints between V1 and V2

Two constraints, A and B
Three Points are possible solutions to both constraints
1 is a quasi stable solution

Temporal Dynamics Analysis

Time analysis:

Consider ideal voltage sources and switches set two intial voltages
Switches are opened at time t=0

Case 1:

$V_1(0) = 0$
$V_2(0) = {V_{\rm DD}}$

$V_1 \rightarrow 0 \Rightarrow \boxed{\mathcal A} \Rightarrow V2 \rightarrow V_{\rm DD} \Rightarrow \boxed {\mathcal B} \Rightarrow V_1 \rightarrow 0$

Case 2:

$V_1(0) = {V_{\rm DD}}/2$
$V_2(0) = {V_{\rm DD}}/2$

$V_1 \rightarrow {V_{\rm DD}}/2 \Rightarrow \boxed{\mathcal A} \Rightarrow V2 \rightarrow {V_{\rm DD}}/2 \Rightarrow \boxed {\mathcal B} \Rightarrow V_1 \rightarrow {V_{\rm DD}}/2$

Case 3:

$V_1(0) = \frac{3}{4} {V_{\rm DD}}$
$V_2(0) = \frac{1}{4} {V_{\rm DD}}$

$V_1 \rightarrow \frac{3}{4} {V_{\rm DD}} \Rightarrow \boxed{\mathcal A} \Rightarrow V2 \rightarrow 0 \Rightarrow \boxed {\mathcal B} \Rightarrow V_1 \rightarrow {V_{\rm DD}}$

$V_1$ is pushed to VDD, system stabalizes
@ ($V_1$ = VDD, $V_2$=0)

Case Quasistable:

In theory, the middle point is also stable
We have assumed a symmetric transfer function and constraints

However, any noise will disrupt the balance.
If $V_1$ is bumped more positive, $V_2$ is pushed more negative and thus $V_1$ is pushed more positive, etc...
Positive Feedback ensure until $V_1=V_{\rm DD}$ and $V_2=0$

Quasi-stable

• Think of of the quasi-stable point in the analogy of balancing a ball on a hill:
  

• Middle point is quasistable and can only be preserved in a noiseless system. Starting points to the left of middle are pushed towards the left and starting points on the right are pushed to the right

• Maintaining Highest Potential Energy:

Quasi-stable point can only be preserved in a noiseless system

Types of Memories

First consider for what types of memories this is relevant:

• Capacitor-Storage Based TODO: Draw a capacitor and switch
• Resistive (e.g. memristor) or other physical state changes
• Latch (Positive Feedback) Based

SRAM

Two Inverter (SRAM):

S-R Latch:

Clocked (Level Sensitive) SR Latch

Clocked D-Latch:

alternative view as extension of clocked SR latch:

Time to Settle

The question of interest is how long does is take to reach a stable state as a function of starting position?

Given $V_A(0)$ how long to reach a stable point?

Given T, a time limit to reach stable point, what is the constraint on $V_A(0)$?

Metastable Cause

Clocked latches can be placed near a metastable state if the clock transistions while data is

The problem is more than complex than "will it settle to the new or old value?"
If placed in a metastable state, the output can be stuck near the quasistable point for a very long time and the following stages will non-deterministically interpret the signal as 1 or 0 depending on thesholds and noise

• Latches are vulnerable to corruption when they are in a state near the quasi-stable point
• Transitions disrupted at the wrong time can be delayed reversed, or even undergo multiple transitions

Synchronized Input Capture:

Assume in the Logic, D1 and D2 represent two conditions that are normally never true but are often opposite in value. This logic is checking if the condition that D1 and D2 are ever true together

Here the output may glitch or become high in error under normal conditions, such as simutanuous tranistions D1:$0\rightarrow1$ and D2:$1\rightarrow0$

Resolution Fanout Point

At some point in the system, parallel resolution must happen that can cause a problem

The same input signal (staring point) can be resolved differently in two components

Temporal Analysis

A generic representation of positive feedback:

Assume the Ideal Amp, at all times $V_B = V_A \cdot A$

Positive Feedback

General behaviour of positive feedback is to accellerate away from a quasi stable point (VA=VB=0)

Negative feedback for comparison:
fast than slow settle at a equilibrium

Analysis

Analyze the temporal voltage change at the input storage capacitor. The voltage value here represents the state of the system

$\frac{dV_A}{dt}=\frac{I}{C}=\frac{V_B-V_A}{R \cdot C}=\frac{A V_A-V_A}{R \cdot C}$

$\frac{dV_A}{dt}=\frac{(A-1) V_A}{R \cdot C}$

$V_A(t) =V_A(0) e^{t\,\,\underbrace{\frac{A-1}{RC}}_K}$

The Question:

Time to reach VDD/2 ?

The Answer:

Approach:
Solve for $t$ in $V_A(t) = V_{DD}/2$
$t=\frac{1}{K} \ln \left(\frac{V_{DD}/2}{V_A(0)} \right)$
This is the time to reach $V_{DD}/2$ given some starting point $V_A(0)$

Time and Voltage Constraint

Bound t to be less than a desired clk-to-Q, i.e. time to resolve, $T_r$ , and find $|V_A(0)|_{\rm min}$

$T_r = \frac{1}{K} \ln \left(\frac{V_{DD}/2}{V_A(0)}\right)$

$V_A(0) = \pm \left(V_{DD}/2\right)^{-1} e^{T_r K}$

$T_r$ and $V_A(0)$ here represent the time and voltage constraints on the input

• Starting values farther from the metastable equilibrium than $|V_A(0)|_{\rm min}$ will resolve quickly

• Starting values closer to the metastable equilibrium than $|V_A(0)|_{\rm min}$ will resolve in a much longer amount of time, and meanwhile are more susceptible to noise corruption

• Nature of Exponentials (Self-similartity)

  • Leads to linear input voltage -> exponential settling time relationship
  • See the mask counts on the next page for 30-min accumulation:

Data as Reference

For the next analysis: instead of viewing the clk as the reference and data timing as the variable:

We will switch and consider the data edge to be the transition

$2|T_W| \approx \frac{2 V_A(0)}{\frac{V_{\rm DD}}{T_{\rm 10-90}}}$
$2|T_W| \approx T_{\rm 10-90} e^{-KT_r}$

• If clock rises in in the data window, the output may not settle in time [eq 3.34]:

$|T_W| = C e^{-KT_r}$

• C is a constant (maybe found empirically), rise-time is a primary component

Mean Time Between Failures

• The Rate of Failure is INVERSELY RELATED TO the mean time between failures

  ${\rm MTBF} = \frac{1}{R\cdot P};R=\frac{N}{T_{\rm span}}$
  R is the data transition rate

• When looking at various documents and datasheets, you may see many alternative forms but with similar underlying form

Actel 1989 ACT-1 Logic:

• Sample Switch Rise Time Constant $C = .5\times10^{-9}$
• Response Time Constant $K = 4.6052 \times 10^{9}$

Page 127
R (rate of transitions) is 1/10th of the clock rate

Mitigating Metastability

1. Faster FF, naturally has narrowed metastability window

2. N-FlipFlops in a row:

Effective Time provided is doubled (2T):
$V_3(2T)=\underbrace{V_2(T)}_{V_3(T)}\underbrace{e^{KT}}_{\text{update}}=V_1(0)e^{KT}e^{KT}=V_1(0)e^{K2T}$
$T_W=Ce^{-2KT}=C\left(e^{-KT}\right)^2$
$P_{\rm fail}\propto \frac{1}{T_W}$
$P_{\rm fail}= \frac{1}{C}\frac{1}{K^2}$ for 2 flip-flops
$P_{\rm fail}= \frac{1}{C}\frac{1}{K^N}$ for N flip-flops

Another Possibility to realize this effect for a multi stage (e.g. master-slave) flip-flop:

3. Metastability-Hardened FF (rather than just a use higher-power fast FF, it would be a low-power flipflop specifically designed with large K)

4. Sample Less Often (Sacrifice Responsiveness)

5. Use Edge-Sharpening Amplifiers at the Input (Fast Transitions)