Understanding Metastability in FPGAs

• In class overview document and especially page 5 for new material (next slide)
  Understanding Metastability in FPGAs ꭝ

• While metastability wasn’t as much a concern for a while, modern lowering of supply voltages increased design sizes (with more chains) and increased data rates are cause for concern especially in life-critical applications.

ꭝ Page 5:
FPGA Architecture Enhancements

Altera uses metastability analysis of the FPGA architecture to optimize the circuitry for improved metastability MTBF. Architecture improvements in Altera’s 40-nm Stratix ® IV FPGA architectures and new device development have improved the metastability robustness results by reducing the MTBF C2 constant.

MTBF and Timing Slack

• Timing slack is the amount of extra time a circuit has to setting according to timing analysis.
• Though sometimes it just excess, wasted time, it can have value mitigating metastability
• Extra slack represents extra time to resolve metastable conditions and can reduce failure rates beyond what a manufacturer has determined to be “acceptable to most”.
• Physical constraints tests should not always be thought of as having a binary outcome interpretation (Fail/Pass), sometimes “failing” simplified physical constraints a little is OK if you understand the impact, and passing with excess can have additional benefits.

ꭝMetastability in Altera Devices Page 5:
Design Optimizations

• "The exponential factor in the MTBF equation means that an increase in the design-dependent tMET [time to settle] value increases a synchronizer MTBF exponentially."
• Assume C2 is 50 ps:
  • 200 ps increase in tMET makes the exponent 200/50 and increases MTBF by exp(4) (more than 50 times)
  • 400 ps increase multiplies MTBF by exp(8) (almost 3k)

• Considering a design with little timing slack and poor MTBF, slowing the clock little (200 ps) can have valued impact ($f_{clk}=500 {\rm MHz} \leftrightarrow f_{clk}=2000 {\rm ps}$)

• For a design with a large amount of timing slack, the reduction in MTBF may not be of value

• Page 4 discuss MTBF Plot

• Brief on Xilinx (discuss “extra” delay”)

MTBF with Multiple Points of Failure

• When considering multiple chains in a system, calculating overall MTFB is done by converting “back” to failure rate FR using inverse, summing rates and inverting back.
• $\rm FR = FR1 + FR2 + FR3 + … + FRN$
  $\frac{1}{\rm MTBF} = \frac{1}{{\rm MTBF}_1} + \frac{1}{{\rm MTBF}_2} + \frac{1}{{\rm MTBF}_3} + … + \frac{1}{{\rm MTBF}_N}$
  $\rm MTBF = \frac{1}{\frac{1}{{\rm MTBF}_1} + \frac{1}{{\rm MTBF}_2} + \frac{1}{{\rm MTBF}_3} + … + \frac{1}{{\rm MTBF}_N}}$
• As a result, the lowest MTBF tends to define the MTBF for the system (if it helps, recall that the upper bound on parallel resistances is the lowest resistance)

ꭝMetastability in Altera Devices Page 5:

• The path with the worst MTBF has a major affect on the design MTBF
• Consider two different designs that have ten synchronizer chains.
  1. ten chains with the same MTBF of 10,000 years
  • MTBF is sum of the failure rates for each chain (failure rate is 1/MTBF); metastability failure rate of 10 chains × 1/10,000 years = 0.001, therefore the design MTBF is 1000 years.
  2. nine chains with MTBF of a million years but one chain with MTBF of 100 years
  • failure rate of 9 chains × 1/1,000,000 + 1/100 = 0.01009 and the design MTBF is about 99 years—just slightly less than the MTBF of the worst chain.