`timescale 1ns / 1ps

module seven_seg_driver (
    input  wire        clk,
    input  wire        reset,
    input  wire [31:0] disp_hex_val, // 32-bit value to display in hex
    output reg  [7:0]  AN,           // Active-low Anode drivers
    output reg  [6:0]  SEG           // Active-low Cathode drivers CA..CG
);

    // 20-bit Refresh Counter for ~1 kHz Multiplexing Rate
    reg [19:0] refresh_counter;
    always @(posedge clk or posedge reset) begin
        if (reset) 
            refresh_counter <= 20'd0;
        else 
            refresh_counter <= refresh_counter + 1'b1;
    end

    wire [2:0] digit_select = refresh_counter[19:17];
    reg  [3:0] current_nibble;

    // Anode Multiplexer
    always @(*) begin
        case (digit_select)
            3'd0: begin AN = 8'b1111_1110; current_nibble = disp_hex_val[3:0];   end // AN0 (DISP1)
            3'd1: begin AN = 8'b1111_1101; current_nibble = disp_hex_val[7:4];   end // AN1
            3'd2: begin AN = 8'b1111_1011; current_nibble = disp_hex_val[11:8];  end // AN2
            3'd3: begin AN = 8'b1111_0111; current_nibble = disp_hex_val[15:12]; end // AN3
            3'd4: begin AN = 8'b1110_1111; current_nibble = disp_hex_val[19:16]; end // AN4 (DISP2 Digit 0)
            3'd5: begin AN = 8'b1101_1111; current_nibble = disp_hex_val[23:20]; end // AN5 (DISP2 Digit 1)
            3'd6: begin AN = 8'b1011_1111; current_nibble = disp_hex_val[27:24]; end // AN6 (DISP2 Digit 2)
            3'd7: begin AN = 8'b0111_1111; current_nibble = disp_hex_val[31:28]; end // AN7 (DISP2 Digit 3)
            default: begin AN = 8'b1111_1111; current_nibble = 4'h0; end
        endcase
    end

    // Hexadecimal to 7-Segment Cathode Decoder (Active Low CA..CG)
    always @(*) begin
        case (current_nibble)
            4'h0: SEG = 7'b100_0000; // 0
            4'h1: SEG = 7'b111_1001; // 1
            4'h2: SEG = 7'b010_0100; // 2
            4'h3: SEG = 7'b011_0000; // 3
            4'h4: SEG = 7'b001_1001; // 4
            4'h5: SEG = 7'b001_0010; // 5
            4'h6: SEG = 7'b000_0010; // 6
            4'h7: SEG = 7'b111_1000; // 7
            4'h8: SEG = 7'b000_0000; // 8
            4'h9: SEG = 7'b001_0000; // 9
            4'hA: SEG = 7'b000_1000; // A
            4'hB: SEG = 7'b000_0011; // b
            4'hC: SEG = 7'b100_0110; // C
            4'hD: SEG = 7'b010_0001; // d
            4'hE: SEG = 7'b000_0110; // E
            4'hF: SEG = 7'b000_1110; // F
            default: SEG = 7'b111_1111;
        endcase
    end

endmodule