`timescale 1ns / 1ps

module uart_to_led_probe (
    input  wire        clk,
    input  wire        reset,
    input  wire [7:0]  rx_data,
    input  wire        rx_empty,
    input  wire        uld_rx_data,
    input  wire [7:0]  tx_data,
    input  wire        tx_empty,
    input  wire        ld_tx_data,
    output reg  [15:0] LED
);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            LED <= 16'd0;
        end else begin
            // Update LED[15:8] with the received byte
            if (!rx_empty && uld_rx_data) begin
                LED[15:8] <= rx_data;
            end
            
            // Update LED[7:0] with the transmitted byte
            if (tx_empty && ld_tx_data) begin
                LED[7:0] <= tx_data;
            end
        end
    end

endmodule