Assignment 7

For this problem the UMBC Red Light policy for AI must be adhered to: (https://my3.my.umbc.edu/groups/provost/posts/155412/2/57c54c0c9cd5cd90136fccec0cc38d27/web/link?link=https://my3.my.umbc.edu/groups/provost/files/14081)

AI Use Not Permitted
All work must be entirely your own. The use of generative AI tools is not allowed
at any stage of the assignment, including brainstorming, experiments, coding,
research, writing, or revision. If you have any questions, feel free to reach out to
me. The use of AI tools will be treated as an academic integrity issue.

All work is expected to be handwritten with steps shown and performed with use only of basic calculator functions as would be practiced for an exam:

• Redo Example 3.4 pg 125 From the High-Speed Digital Design (1 pt) I posted a book section for class: High-Speed-Digital-Design_Section3pt11.pdf ( https://drive.google.com/a/umbc.edu/file/d/0B5MWE1meYfDbc0RHQmh4LUVnMVlSSmFqRlZnVFg3NXd1bG9j/view?usp=sharing )
• Work through the example up to calculating the MTBF for 35 MHz and 30MHz – submit your work and answers.
• Additionally, derive and report what would be the result of increasing the delay of the inverters by 1 ps in each case. Discuss the relationship of the 4 results considering both absolute and relative comparisons of values and changes.

Write answer by-hand:

Explain how a PLL-based circuit on an FPGA would be configured to generate a 6.25 Mhz and a 3.75 Mhz clock from a 50 MHz clock input. Use the IntelFPGA/Altera example provided in the lecture notes as an example. Provide TWO different configurations that would work.

Write this answer by-hand:

• a. Explain how a write enable/strobe can be used to communicate 16-bit words between clock domains more safely.
• b. Does the choice of a grey code increase mean time between failures if transferring a set of random numbers from one clock domain to another (CDC)?

Write answer by-hand:

Assume that some synchronous digital system operates at 100 MHz and needs to sample an asynchronous user input from a button selection panel that has three buttons: A,B, and C. The user will only ever press one button at a time, and will always release one button before pressing another. It is significant that synchronous digital system is provided information about both

1. if any button is being pressed or not and
2. which button is pressed if any.

Consider two encoding proposals for conveying the button status to be sampled and thus conveyed into the domain of a synchronous circuit:

if (A_pressed) begin
   enc = 3'001;
end else if (B_pressed) begin
   enc = 3'010;
end else if (C_pressed) begin
   enc = 3'100;
end else begin
   enc = 3'111;
end

if (A_pressed) begin
   enc = 3'1_00;
end else if (B_pressed) begin
   enc = 3'1_01;
end else if (C_pressed) begin
   enc = 3'1_10;
end else begin
   enc = 3'0_11;
end

• a. Discuss which of these that you would consider to be a better encoding to avoid metastability during overall operation. Provide specific justification.
• b. if the system frequency is decreased to 10 MHz (but the human does not change its behavior), how does is the probability of failure on the first press changed and how is the MTBF for the system affected? What additional information would you need to quantify (provide a numerical answer) that change?

Write this answer, showing work, by-hand:

Assume that a UART scheme is used to send one-way data using 1 stop bit and 12 data bits. Assume that setup and hold time are 1 ns for the given receiving system and the given received data edge slope. If the expected sending baud rate is 10 mbs, what is the range of actual baud rates from the sender that would be acceptable? What would be a reasonable clock rate for the receiver to use internally to oversample the data?

First, complete the tutorial the tutorial ./asgmt7_tutorial.html which includes, an integrated logic analyzer, virtual IO, generation of multiple clocks using a PLL, and use of external DDR memory.
The completed design has essential two separate designs, a communication framework and a FSM accessing external memory.
Modify the completed design so that memory can be read and written using Python software.
The python software should send two types of command packets:

for a write packet:

BYTE0: SEQ(5=bit), 1 (3-bit)
BYTE1: ADDRLOWBYTE
BYTE1: ADDRHIGHBYTE
BYTE2: DATAHIGHBYTE
BYTE3: DATALOWBYTE

for read:

BYTE0: SEQ(5-bit), 0 (1-bit)
BYTE1: ADDRLOWBYTE
BYTE1: ADDRHIGHBYTE

The sequence value, SEQ , should be incremented with each command packet sent.

After sending a write command, python should read back 1 word that is a copy of the first byte sent, which include the command and the sequence id
After sending a read command, python should read back 1 word that is a copy of the first byte sent followed by 2 bytes of data

You should create a case-statement based FSM (start from the ones already in top.sv, but merge/modify them) to control the components in the system and interface with the python code appropriately. Test the design by writing to and reading from multiple memory locations.