Discussion SystemVerilog

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References

[1] IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language - Redline https://ieeexplore.ieee.org/document/5985443
[2] http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf

To use SystemVerilog, when adding a new file to a project select SystemVerilog instead of Verilog the file extension will be .sv instead of .v

module statemachine_vs(out,finished,
                       skip_to_finish,
                       ,clk,rst);
  input clk;
  enum logic [1:0] {S_INIT=2'd0,
                    S_WAIT=2'd1,
                    S_FINISH=2'd2} CS,NS;   
  logic [7:0] x,_x;
  output logic finished;
  logic _finished;
  input      skip_to_finish;
  input      rst;
  output logic out; 
  logic _out;
   
  logic rst_n;
  not myinv(rst_n,rst);

  always_ff @ (posedge clk,negedge rst_n) begin
    if (rst_n==0) begin
      CS<=S_INIT;
    end else begin   
      CS<=NS;
    end
  end

  always_ff @ (posedge clk,negedge rst_n) begin
    if (rst_n==0) begin
      //no resets required
    end else begin   
      finished <= _finished;
      out <= _out;
      x <= _x;
    end
  end

  
  //Next State Logic
  always_comb begin
    NS = CS;
    case(CS)
      S_INIT:   NS = S_WAIT;
      S_WAIT:   if (skip_to_finish) NS=S_FINISH; 
                else if (x==0) NS=S_FINISH; 
                else NS=CS;
      S_FINISH: NS = S_INIT;
    endcase  
  end

  //Extended State Registers Combinatorial Logic
  always_comb begin
    _x = 'x;
    case(CS)
      S_INIT: _x = 4;
      S_WAIT: _x = x-1;
    endcase  
  end

  //Registered Output Logic Based on CS,NS
  always_comb begin
    _finished = 0;
    _out = 0;
    case (NS)
      S_INIT: begin
        _out = 0;
        if (CS == S_FINISH) begin 
          _finished=1;
        end else begin
          _finished=0;
        end
      end
      S_WAIT: begin
        _out = 0;
        _finished = 0;
      end
      S_FINISH: begin
        _finished=0;
        if (skip_to_finish) begin
          _out=0;
        end else begin              
          _out=1;       
        end
      end
    endcase // case (CS)
  end // always @ 
  
endmodule // test

Enumerated Types

• keyword enum

  enum logic [1:0] {S_INIT=2'd0,
                    S_WAIT=2'd1,
                    S_FINISH=2'd2} CS,NS;
  

  enum logic [1:0] {S_INIT,S_WAIT,S_FINISH} CS,NS;
  

• Useful for State Variables

• will display in waveform viewers, statemachine viewers

• can print with %s and .name()

  • Example to print name and value of current state:

    $display( "%s : %d\n", CS.name, CS );
    

• [2] 10.1 Enumerated types

new combinatorial always

• use keyword always_comb in combinatorial blocks were always @ (*) typically used
• infers sensitivity list
• enforces memoryless logic, tools should check that only combinatorial logic is inferred
  Example Error from Quartus

Warning (10230): Verilog HDL assignment warning at xx.sv(49): truncated value with size 32 to match size of target (8)
Warning (10240): Verilog HDL Always Construct warning at xx.sv(32): inferring latch(es) for variable "_x", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at xx.sv(32): inferring latch(es) for variable "_finished", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at xx.sv(32): inferring latch(es) for variable "_out", which holds its previous value in one or more paths through the always construct
Error (10166): SystemVerilog RTL Coding error at xx.sv(32): always_comb construct does not infer purely combinational logic.

• Example Use

  always_comb begin
    _x = 'x;
    case(CS)
      S_INIT: _x = 4;
      S_WAIT: _x = x-1;
    endcase  
  end
  

• prevents writing to output variables from other processes
• in simulation called once at time zero after initial and always procedures
• [2] 10.2 @* and always_comb
• no blocking timing controls allowed

new sequential always

• always_latch

  • like always_comb but instead software should check if a latch is inferred

• always_ff

  • output variables should not be written to from any other processing block
  • one and only one event control (e.g. always_ff @(posedge clk or negedge rst_n) , no blocking timing controls allowed

final

• final procedure keywork
  • like initial procedures, but instead are called at the end of a simulation instead of at the begining
  • keyword use:

  final begin $display("Simulation Ended"); end
  

logic

• New Data Type Declaration Keyword logic
  • logic , can generalize reg and wire
  • allow to assign from procedural and continuos assignments and port connections
  • in non-system Verilog would default to reg
  • many examples shown in sample code

Implicit port connections

• New shorthand for Implicit port connections

• use .* in instantiation to connect ports of module to variables names in the same scope

• useful for testbenches, since it is common to create several signals with the same name as the ports of the DUT

• examples:

  stamachine DUT(.*);
  

  stamachine DUT(.rst(~rst_n),.*);
  

• [2] 11.0 Implicit port connections

String

• new type and keyword string
• useful for simulation code
  • processing IO in testbench code,
  • reading and writing ASCII data from file
  • manipulation of ASCII data in testing and simulation code
  • generation of print messages for simulation code
• elements are of type byte (a new 2-state variable type)
• assumed to be null-terminated, so null characters \0 are removed from string literals "123\0123" is "123123"

Two-State Variables

• can encode a 1/0, not metalogic values x and z
• supports more efficient simulation of large designs
• includes bit, byte, shortint, int, longint

Metalogic Assignment Shorthand

• 'x and 'z
• Examples:

  • dest<='x; 
    

  • dest='z; 
    

• no need to specify number of bits

Separate Compilation

• new keyword extern
• supports separate compilation

  extern module statemachine(out, finished,
                           skip_to_finish,
                           clk,rst);
  

Unique and Priority

good reference:
https://www.verilogpro.com/systemverilog-unique-priority/

unique keyword

• can be placed before if (if else, else), case, casez, casex
• declares that only one case will be matched at a time
  • cases can be evaluated in parallel
  • allows checking for multiple matches
    • a verification or simulation tool can verify this assertion and generate messages where it is violated
• declares that ALL cases are covered
  • any cases not covered are assumed to be DON'T CARE
  • allows checking for unmatched cases
    • in simulation an unmatched case will generate a warning (for if statements, provide else prevents this )

unique0 keyword in SystemVerilog 12 only checks for multiple matches but not unmatched

priority keyword

• can assume priority in order of cases, generate warning if unmatched case (for if statements, provide else prevents this )