Reconfigurable System Design Discussion 02: Quartus and Modelsim

• Dr Ryan Robucci and Saad Rahman
  Updated September 3, 2020

Objective

1. Introduction to Quartus Lite
   1. Download
   2. Installation
2. Introduction to De1-SoC board
   1. Board description
   2. Settings of FPGA Configuration Mode
   3. Important Pin locations
3. Demonstration
   1. Creat a New Project
   2. Simulation
   3. Quartus IP creation and simulation

Introduction to Quartus Lite

• Download : To download Quartus Prime Lite Edition 18.1. Click here. For reference,see the following figure.

  

  Figure 1
  • Installation : Now extract the .tar package with any compression software (7zip or WinRAR). Then click on setup file to start install. Follow The process of install based on pictures.

  

  

  

  

  

  

  

  

  

Introduction to De1-SoC board

• Board description : The layout of the board is provided in the following figure.

  

  

Settings of FPGA Configuration Mode : When the DE1-SoC board is powered on, the FPGA can be configured from EPCQ or HPS. The MSEL[4:0] pins are used to select the configuration scheme. It is implemented as a 6-pin DIP switch SW10 on the DE1-SoC board, as shown in the following figure.

The other configuration mode are described in the following table.

• Important Pin locations : Pin assignments of most used component of the board i.e Clock, Switches, Pushbuttons and LEDs are provided in the following table . For more detailed information download

Demonstration

Create a New Project

• In main window menu: File->New...
  

• Then click on New Quartus Prime Project in the opened window
  

• click on the Next Button
  

• Define your project directory and the name of project
  

• Check the Empty project dialouge and then Next
  

• Add files if you have, otherwise click Next
  

• You will now need to enter information about the FPGA:
  for example V SE 5CSEMA5F31C6N(our SOC board)
  

• Leave all option None
  

• Hit Finish
  

• Result
  

Now add a verilog file to project by using File-> Verilog HDL File

write the following code in the new verilog file and save the file with the name of verilog module (here is add_multiply)

module add_multiply(input signed [3:0] a,b,input mode,output[8:0]result);

assign result = (mode) ? a + b : a * b ;  

endmodule

Simulation

• First a add a new verilog file to project and write your testbench:

`timescale 1ns/1ns

module add_multiply_tb;

	// Inputs
	reg [3:0] a;
	reg [3:0] b;
	reg mode;

	// Outputs
	wire [8:0] result;

	// Instantiate the Unit Under Test (UUT)
	add_multiply uut (
		.a(a), 
		.b(b), 
		.mode(mode), 
		.result(result)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		b = 0;
		mode = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		
		a = 7;
		b = 4;
		#100;
		mode = 1;
		#100;
		$finish;

	end
      
endmodule

• Configuring Modelsim : To configure Quartus to use Altera-Modelsim as the simulator, first create a new project (or open an existing one) and go to Assignments > Settings > EDA Tool Settings.Make sure “Modelsim-Altera” is selected as the tool as shown below (make sure to click Apply then OK if you made any changes).

Next go to Tools > Options > General > EDA Tool Options sure that the path next to Modelsim-Altera is configured correctly. If you installed Quartus II with Altera-Modelsim the path should be similar to the one shown in the figure (i.e. on Windows:“C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem”), otherwise you will need to browse to where you installed Altera Modelsim and point it to the win32aloem directory.

go to Assignments > Settings > EDA Tool Settings > Simulation check the Compile test bench dialog and click Test Benches button and then click New..

Then, in the openned window, specify your test bench and add test bench file from the project directory to software. Click OK and finally Apply in simulation setting page:

• compile project:* hit compile design bottom(Ctrl + L) in the task bar.
  

• Open Altera-Modelsim: To open altera-modelsim go to Tools > Simulation Tool > RTL Simulation. This should open up Altera-Modelsim.

• Observe your simulation waveforms : You may have to adjust the window to see your waveforms.

• hint: to have a Gate Level Simulation go Tools > Simulation Tool > Gate Level Simulation

Quartus IP creation and simulation

In this section we will show how to use Quartus IP Catalog. We start by crating a simple module.

Steps :

1. Open Quartus Prime. Create a empty project and specify the name of the project and top-file as ip_test.
2. When you're in the main Quartus Prime window, at the right portion you'll see a tab named IP Catalog. We'll choose our IP from here.
3. From IP Cataloggo to Library -> Basic Functions -> Arithmetic. Double click on ALTSQRT. A new window like Figure 31 will appear. Give the name as ip_sqrt and press OK.

1. Then the SQRT IP parameter window like Figure 32 will appear. Edit these configurations as Figure 2 and hit ``Next >`.

5. A summary window like Figure 33 will appear,Check the .bsf and .v files and then hit Finish to create the IP.

6. In the Project Navigator (on the top left hand side of software) set the setting on Files. Now you can see the ip core ip_sqrt.qip. Go to sub-level, and open ip_sqrt.v. Now the inputs and outpus of ip core can be seen.
   

7. Add a verilog source to project with name of top module which you have already named it. Copy the inputs and outputs of ip core into this file.

8. Make an instantiation of ip core in your top module.

9. Add your test bench file in your project and configure required setting.

module ip_test(radical, q, remainder);
	
	input	 [7:0]  radical;
	output [3:0]  q;
	output [4:0]  remainder;
	
	ip_sqrt	uut(.radical(radical),.q(q),.remainder(remainder));
	
endmodule

`timescale 1ns/1ps

module ip_test_tb();

	reg  [7:0]  radical;
	wire [3:0]  q;
	wire [4:0]  remainder;

	ip_test uut(.radical(radical),.q(q),.remainder(remainder));
	
	
	initial
	begin
		radical = 8'd0;
		
		# 100
		radical = 8'd72;
		
		# 100
		radical = 8'd36;
		
		# 100
		
		$finish;
	end
	
endmodule

10. Hit Start Analysis and Synthesis button.

11. After finishing the analysis and synthesis successfully, go to Tools -> Run Simulation Tool -> RTL Simulation . Then the ModelSim window will load.

    
    You can also run a gate level simulation:
    Tools -> Run Simulation Tool -> Gate Level Simulation