Assignment 3 : CMPE 691 Fall 2026

UMBC
Professor: Ryan Robucci

Due Sept 29

Use SystemVerilog where appropriate.

P1

Second Edition Book Problem 4.2. Draw the CFG and the DFG of the program in Listing 4.2. Include all control dependencies in the CFG. Include the data dependencies for the variables a and b in the DFG.

Listing 4.2 for Problem 4.2

int count(int a, int b){
    while (a<b)
        a = a * 2;
    return a + b;
}

P2

Second Edition Book Problem 4.3. Design a datapath in hardware for the program shown in Listing 4.3. Allocate registers and operators. Indicate control inputs by the data-path, and condition flags generated by the datapath.

Listing 4.3 for Problem 4.3:

unsigned char mysqrt( unsigned int N){
    unsigned int x,j;
    x= 0;
    for( j = 1<<7; j!= 0; j>>=1){
        x = x + j;
        if ( x*x > N)
            x = x - j;
    }
    return x;
}

P3

Second Edition Book Problem 5.7 Develop the state-machine requested using SystemVerilog. Present commented code, commented testbench code, and simulation results.

P4

Second Edition Book Problem 5.8 Develop the state-machine requested using SystemVerilog. Present commented code, commented testbench code, and simulation results.

P5 Statemachine Styles with SystemVerilog

Use SystemVerilog.

Of course present commented code, commented testbench code, and simulation output in your submission.
Create a single state-machine module to find the a pattern of an 8-bit input stream – the characters “boab” (98,111,97, 98) – and produce an output signal when an end ’b’ is found within an instance the pattern. Once an end ’b’ in the a pattern is found, the output signal should stay high until the input ack signal goes from low to high (for instance, if the ack signal was high when the ’b’ arrived it must go low first). Your state machine should not start searching for the pattern again once it is found until the ack signal falls back to low. It should start the searching the input again on the same cycle ack is first low (i.e. a new starting ’b’ in the same cycle as the first low value value of ack should be noticed).

    module PatternDetector (input [7:0] data, 
                            input reset_sync, 
                            input clk, 
                            input ack, 
                            output found_pattern)

For Combinational Outputs:

For registered outputs (found_pattern cannot coincide with the final b):

You need to implement the module according to the descriptions below with reference to the styles described in the slides and in sections 2.1,2.2, and 2.3 (http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf)

archive link: https://web.archive.org/web/20250109011350/http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf

( a ) From Paper Section 2.1 – Two always block style with combinational outputs. Your implementation should be able to output a high value in response to the found_pattern signal within the same clock cycle that the final “b” input arrives, earlier than the next two registered-output implementations. It should also goto low in response to the ack signal immediately.
( b ) From Paper Section 2.3 – Three always block style with registered outputs. This and the next registered-output style implementation should produce the exact same responses.
( c ) From Paper Section 2.2 – One sequential always block style with registered outputs. This and the previous registered-output style implementation should produce the exact same responses.
( d ) From Paper Section 2.1 – Two always block style with combinational outputs. Modify your combinatorial-output state machine so that its output matches the like the registered output versions with respect to the value of the output at various clock edges.

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