Submission (5 Questions) Due Nov 15th
Redo Example 3.4 pg 125 From the High-Speed Digital Design (1 pt) I posted a book section: High-Speed-Digital-
Design_Section3pt11.pdf ( https://drive.google.com/a/umbc.edu/file/d/0B5MWE1meYfDbc0RHQmh4LUVnMVlSSmFqRlZnVFg3NXd1bG9j/view?usp=sharing )
Work through the example up to calculating the MTBF for 35 MHz and 30MHz – submit your work and answers.
Additionally, what would be the result of increasing the delay of the inverters by 1 ps in each case?
Explain how a PLL-based circuit on an FPGA would be configured to generate a 6.25 Mhz and a 3.75 Mhz clock from a 50 MHz clock input.
Assume that a UART scheme is used to send one-way data using 1 stop bit and 12 data bits. Assume that setup and hold time are 1 ns for the given receiving system and the given received data edge slope. If the expected sending baud rate is 10 mbs, what is the range of actual baud rates from the sender that would be acceptable?
What would be a reasonable clock rate for the receiver to use internally to oversample the data?
a. Complete Discussion 9 (https://eclipse.umbc.edu/robucci/cmpeRSD/discussions/discussion09) and provide a screenshot of the output
b. Explain why certain paths are unconstrained and which ones were so.
c. In the timing analysis, is it considered to be static or dynamic timing analysis?
d. Explain the timing for the fifo to fill.
e. Why does the data output change by 2?
Increase the write clock to be 30 MHz by modifying the PLL.
Modify the FIFO depth to 128 instead of 256.