Lecture 11 Metastability

• ꭝ High Speed Digital Design: A Handbook of Black Magic 1st Edition by Howard Johnson (Author), Martin Graham (Author)

• consider a chain of digital gates
• signal corruption model: ideal gates with noise sources
• desire proper interpretation of binary values in presence of noise

• Sources of Noise:
  • 1) Electronic Thermal Noise
  • 2) Power/Ground Current (through supply resistance)
  • 3) Fast Signals in the System (large dI/dt induces drops in supply inductance)
  • 4) Signal Coupling: Mutual Cap. and Mutual Inductive
  • 5) Ringing (will draw in-class if required)
  • 6) Temperature Differences between components affecting threshold voltages

(3-5 are especially important for fast systems)

Additionally, manufacturing between devices can introduced fixed noise, which may be exhibited as device-specific offsets

• Noise margins ensure correct digital operation, maintaining the digital abstraction
• Require voltage constraints on inputs, and outputs to satisfiy input constraints for the downstream gate even in the presence of noise
• The difference between the output and input constraint are known as the **Noise Margin**s
• Noise Margin High is the margin for logical high: \(V_{\rm NNH}=V_{\rm OL}-V_{\rm IH}\)
• Noise Margin Low is the margin for logical low : \(V_{\rm NNL}=V_{\rm IL}-V_{\rm OL}\)

• Digital Gates restore weak values by the low gain in the valid input regions.
  • Typical in this context to denote gain of -1 (slope=-1) as boundary of low gain and high gain
• Inputs in the valid regions safely produce valid outputs even when corrupted with noise
• Inputs in the invalid region can produce high or low outputs with moderate noise

• Some corruption is proportional to voltage swings
  • Examples:
    • larger transition \(\rightarrow\) larger ringing
    • larger transition \(\rightarrow\) larger disturbance on neighboring signal lines

• Noise Performance Figure of Merit: Ratio of Noise Margin to Voltage Swing is a useful figure of merit (FOM)

For example: for two logic families, noise margins that are proportional to the power supply level may perform roughly the same \({\rm FOM} = \frac{\rm Noise\ Margin}{\rm Voltage\ Swing} = \frac{V_{OH}-V_{IH}}{V_{OH}-V_{OL}}\) or \(\frac{V_{IL}-V_{OL}}{V_{OH}-V_{OL}}\)

• for those that like %: magnitude the noise may be quantified as a percentage of full voltage range

• Registers tend to have voltage as well as specific timing requirements for the inputs

• Setup and Hold

  

• If violated, may get
  • Old Data
  • New Data

  • Metastable Output

    • Not conform to voltage specifications
    • May change in middle of clock period (multiple output transitions triggered by the clk)

    Possible Output transitions when expected is 0->1:

    

• Clock Domain Crossing arises from the need to communication between Multiple Clock Domains
• You have learned in sync. design in one clock domain

• Having Multiple Clock Domains means Clock Domain Crossing must be considered

  

Not all signals arise from a clock domain at all, such as physical, real-world inputs

A problem arises at a fanout point, where mutiple interpretations are performed in parallel. If the voltage is not a valid high or valid low, inconsistent interpretations can result.

Consider that an inverter represents contrain on allowed input, output (\(V_1\),\(V_2\)) relationships:

The graph on the right shows how V2 is driven.

Consider another inverter with the input and output connections are exchanged:

The graph on the right shows how V1 is driven.

Consider a coupled set of inverters, setting constraints between V1 and V2

Set of constraints and underlying drive on V1,V2:

Two constraints, A and B Three Points are possible solutions to both constraints 1 is a quasi stable solution

Time analysis:

Consider ideal voltage sources and switches set two intial voltages Switches are opened at time t=0

First consider for what types of memories this is relevant:

• Capacitor-Storage Based

  • Capacitor and switch:

  

• Resistive (e.g. memristor, magnetic storage) or other physical state changes
• Latch (Positive Feedback) Based

The question of interest is how long does is take to reach a stable state as a function of starting position?

Given \(V_A(0)\) how long to reach a stable point?

Given T, a time limit to reach stable point, what is the constraint on \(V_A(0)\)?

• Clocked latches can be placed near a metastable state if the clock transitions while data is

• The problem is more than complex than "will it settle to the new or old value?" If placed in a metastable state, the output can be stuck near the quasistable point for a very long time and the following stages will non-deterministically interpret the signal as 1 or 0 depending on thresholds and noise

• Latches are vulnerable to corruption when they are in a state near the quasi-stable point
• Transitions disrupted at the wrong time can be delayed reversed, or even undergo multiple transitions

Assume in the Logic, D0 and D1 represent two values that are sampled and sent into an AND gate.

Here the AND output may glitch and become low in error if the inputs change at a disallowed time.

At some point in the system, parallel resolution can cause a problem

The same input signal (staring point) can be resolved differently in two components

A generic, 1st-order representation of positive feedback:

Assume the Ideal Amp, at all times \(V_B = V_A \cdot A\)

Bound t to be less than a desired clk-to-Q, i.e. time to resolve, \(T_r\) , and find \(|V_A(0)|_{\rm min}\)

\(T_r = \frac{1}{K} \ln \left(\frac{V_{DD}/2}{V_A(0)}\right)\)

\(V_A(0) = \pm \left(V_{DD}/2\right)^{-1} e^{T_r K}\)

• Starting values farther from the metastable equilibrium than \(|V_A(0)|_{\rm min}\) will resolve quickly
• Starting values closer to the metastable equilibrium than \(|V_A(0)|_{\rm min}\) will resolve in a much longer amount of time, and meanwhile are more susceptible to noise corruption
• Nature of Exponentials (Self-similarity)

• Leads to relationship: linear input voltage -> exponential settling time

• See the mask counts on the next page for 30-min accumulation:

  ꭝJohnson and Graham

  --

\[\boxed{T_r \lt \frac{1}{F_{\rm clk}} - T_{PD}} \rightarrow T_W=Ce^{-K \boxed{T_r}}\]

\(T_{\rm W}\) defines the window of error [eq 3.36] that helps define setup and hold time requirements and thus allowed combinatorial propagation delays

• Probability of Failure Per Data Transition:

\[ P = \frac{2T_W}{T_{\rm CLK}} = 2F_{CLK}Ce^{-KT_r} \] (this is the likelihood that a random transition falls in a disallowed epoch)

• Assume
  • in given time span \(T_{\rm span}\) there are \(N\) data transitions expected
  • each transition having probability P of causing a failure,
• The expected # of failures in that timespan

\[N\cdot P \text{ failures in timespan } T_{\rm span}\]

• The rate of failure is the rate of data transitions times the probability of a given transition causing a failure

\[\frac{N}{T_{\rm span}} \cdot P = \rm Expected\,Rate\,of\,Failure\]

• The Rate of Failure is INVERSELY RELATED TO the mean time between failures

  \[{\rm MTBF} = \frac{1}{R\cdot P};R=\frac{N}{T_{\rm span}}\] R is the data transition rate

• When looking at various documents and datasheets, you may see many alternative forms but with similar underlying form

Actel 1989 ACT-1 Logic:

• Sample Switch Rise Time Constant \(C = .5\times10^{-9}\)
• Response Time Constant \(K = 4.6052 \times 10^{9}\)
• ꭝPage 127: R (rate of transitions) is 1/10th of the clock rate: