FISCAL: Firmware identification using side-channel power analysis
Deepak Krishnankutty, Ryan Robucci, Nilanjan Banerjee and Chintan Patel
IEEE 35th VLSI Test Symposium (VTS), 2017
BibTeX
@INPROCEEDINGS{fiscal2017,
author={D. Krishnankutty and R. Robucci and N. Banerjee and C. Patel},
booktitle={2017 IEEE 35th VLSI Test Symposium (VTS)},
title={FISCAL: Firmware identification using side-channel power analysis},
year={2017},
volume={},
number={},
pages={1-6},
keywords={dynamic programming;firmware;instruction sets;pattern classification;pipeline processing;principal component analysis;security of data;FISCAL;PCA;classification;code sequence;dynamic programming algorithm;firmware identification using side-channel power analysis;general purpose pipelined computing platform;instruction execution sequences;malicious code insertion detection;power supply pins;power-supply templates;principal component analysis;template matching;Field programmable gate arrays;Hardware;Pins;Power supplies;Principal component analysis;Registers;Transient analysis},
doi={10.1109/VTS.2017.7928948},
ISSN={},
month={April}}
Conference Paper
AR: TBD
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Firmware Instruction Identification Using Side-Channel Power Analysis
Deepak Krishnankutty, Ryan Robucci, Nilanjan Banerjee and Chintan Patel
IEEE International Symposium on Hardware-Oriented Security and Trust, McLean, VA, May 2016
Hardware Demo
AR: TBD
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Post-Layout Estimation of Side Channel Power Supply Signatures
Sushmita K Rao, Deepak Krishnankutty, Ryan Robucci, Nilanjan Banerjee and Chintan Patel
IEEE International Symposium on Hardware-Oriented Security and Trust, McLean, VA, May 2015
BibTeX
@INPROCEEDINGS{host2015,
author={S. K. Rao and D. Krishnankutty and R. Robucci and N. Banerjee and C. Patel},
booktitle={2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)},
title={Post-layout estimation of side-channel power supply signatures},
year={2015},
volume={},
number={},
pages={92-95},
keywords={cryptography;estimation theory;integrated circuit layout;logic testing;power consumption;power supply circuits;security;DES cryptosystem;DPA;DfS;IC;SPICE simulation;anomaly detection;cipher-text;design-for-security;differential power analysis;encryption core;hardware trojan;integrated circuit;logic operation;malicious hardware insertion;plaintext;post-layout estimation;power consumption correlation;power supply measurement;power supply tracing;practical attack;prefabrication power consumption prediction;side-channel based attack;side-channel power supply signature estimation;Correlation;Hardware;Integrated circuits;Power supplies;SPICE;Security;Transient analysis;Hardware Security;Power Supply analysis;Side-channel attacks;Trojan Detection},
doi={10.1109/HST.2015.7140244},
ISSN={},
month={May}}
Conference Paper
AR: TBD
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Monitoring Instruction Level Events Via Power Supply Side-Channel Leakage Analysis
Deepak Krishnankutty
PhD Proposal Defense, University of Maryland Baltimore County, April 02, 2018
BibTeX
@misc{DeepakPhDProposal2018,
title = {{PhD Proposal:} Monitoring Instruction Level Events Via Power Supply Side-Channel Leakage Analysis},
howpublished = {\url{http://eclipse.umbc.edu/talks/Deepak_proposal_slideset.pptx}},
note = {Accessed: 2018-04-04}}
PhD Proposal Defense
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SIDE-CHANNELs for CROSS-LAYER SECURITY: A HARDWARE PERSPECTIVE
Ryan Robucci
6th International workshop on cybersecurity, JR Hakata city, Fukuoka, Japan, Jan 22, 2018
BibTeX
@misc{RobucciJapanTalk2018,
title = {SIDE-CHANNELs for CROSS-LAYER SECURITY: A HARDWARE PERSPECTIVE},
howpublished = {\url{http://eclipse.umbc.edu/talks/robucci_SIDE-CHANNELs_For_Security.pptx}},
note = {Accessed: 2018-04-04}}
Talk
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