**Course Title** : Programmable Logic Devices
**Course Number** : CMPE 415
**Credits**: 3.00
**Description**: This course covers the concepts, structure and programming characteristics of programmable logic devices such as PLDs and FPGAs. Hardware Description Languages (HDLs) are used to create designs that are tested on FPGA devices.
**Prequisite ** : You must complete CMPE 310 with a grade of C or better.
Dr. Ryan Robucci
Assistant Professor
Email: robucci@umbc.edu
Department of Computer Science and Electrical Engineering
University of Maryland Baltimore County
1000 Hilltop Circle
Baltimore, MD, 21250
Office: ITE 319 Office Hours: TBD
Phone: 410-455-3549
** Meeting Time ** TuThu 2:30-3:45 ** Teaching Assistants and Graders ** : * TA: Ambrin Begam Riaz Ahmed - umbc email: ambrinr1 **Syllabus** : PDF


| Date | Event | Description/Reading | Assignments and Due Dates |------------------|---------------------|----------------------------------------------------------------------------------------------------------------------------|------------------------------------------- |Aug 30 | First Lecture | Course Introduction, [Intro to FPGAs](./attachments/Lecture00.pdf) | Reading for Next Class Copyright Elsevier, for class use only| |Sept 5 | Lecture | [FPGA Technology I](./attachments/Lecture01_FPGATechI.pdf) | -- | |Sept 6 | Lecture | [FPGA Technology II](./attachments/Lecture02_FPGATechII.pdf) **use same password as for the reading** | -- | |Sept 11 | Lecture | [Introduction Verilog I](./attachments/Lecture04_IntroVerilogI.pdf) [Introduction Verilog II](./attachments/Lecture04_IntroVerilogII.pdf)[Introduction Verilog III](./attachments/Lecture04_IntroVerilogIII.pdf) | [Vivado Installtion](./hw1/vivado.html), [HW1](./hw1/index.html) |{warning} Sept 18 | Due Date | | Submit HW1 (Submission Instructions Posted on Piazza)| |Sept 19 | HW2 Assigned | | [HW2](./attachments/HW2.pdf) Due Oct 4, [simulation instructions](./simulation) | |Sept 20 | Lecture | [Events Timing and Testbenches](./attachments/Lecture05__Events_Timing_Testbeches.pdf) | -- | |Sept 25 | Lecture | [Debugging and Monitoring](./attachments/Lecture06__Debugging_and_Monitoring_Statements.pdf) | -- | |Sept 27 | Lecture | [Full and Parallel Case](./attachments/Lecture07__Full_and_Parallel.pdf) including Differences in Simulation and Synthesis | -- | |{warning} Oct 4 | Due Date | | Submit HW2 | | Oct 4 | Lecture | [Suggested Coding and Design Practices](./attachments/Lecture08__Suggesting_Coding_and_Design_Practices.pdf) | -- | | Oct 17 | Lecture | [Details of Operations and Variables](./attachments/Lecture09__Operators_Operands_Variables_Literals.pdf) | -- | | Oct 5 | HW3 Assigned | | [HW3](./hw3) Due Oct 15 | |{warning} Oct 15 | Due Date | | Submit HW3 | |{warning} Oct 18 | Quiz 2 | | -- | | Oct 19 | HW4 Assigned | | [HW4](./hw4) Due Oct 25/29 | | Oct 23 | Lecture | [Synthesis and Loops, Single Assignment Code](./attachments/Lecture10__Synth_and_Loops.pdf) | -- | | Oct 24 | Lecture | [Case-Statement-Based FSM I](./attachments/Lecture11__FSM_I.pdf) | -- | |{warning} Oct 25 | Due Date | | Submit HW4 Inital Report | |{warning} Oct 29 | Due Date | | Submit HW4 | | Oct 30 | Lecture | [Case-Statement-Based FSM II](./attachments/Lecture12__FSM_II.pdf) | -- | |{warning} Nov 1 | Exam | | -- | | Nov 2 | HW5 Assigned | | [HW5](./hw5) | | Nov 28 | Lecture | [Timing, Testbenches and More Advanced Verilog](attachments/Lecture13.pdf) | -- | |{warning} Nov 9 | Due Date | | Submit HW5 initial submission | |{warning} Nov 19 | Due Date | | Submit HW5 project submission | |{warning} Nov 20 | Due Date | | Submit HW5 report submission | | Nov 29 | HW6 Assigned | | [HW6](./hw6) | | Dec 4 | Lecture | [FPGA Developement](attachments/Lecture14.pdf) | -- | | Dec 11 | Lecture | [FPGA Tech III](attachments/Lecture03_FPGATechIII.pdf) | -- | |{warning} Dec 11 | Due Date | | Submit HW6 | |{warning} Dec 12 | Due Date | | Submit HW6 report| |{warning} Dec 13 | Final Exam | 1:00-3:00 https://umbc.app.box.com/v/fall2018regularfinalexams | -- |
Date Event Description Assignments and Due Dates
Aug 31 First Lecture Course Introduction, Intro to FPGAs Reading for Next Class Copyright Elsevier, for class use only
Sept 5 Lecture FPGA Technology I Slides *use same password as for the reading
Sept 7 Lecture FPGA Technology II Slides *use same password as for the reading
Sept 12 Lecture FPGA Technology III Slides *use same password as for the reading
Sep 13 Wed Last day to Drop w/o a grade of "W"
Sept 14 Assignment HW 1 Due Thursday Sept 21th
Sept 14 Lecture Introducing Verilog HDL
Sept 26 Assignment HW 2 Due Tues Oct 5th
Sept 28 Lecture Events, Timing, Teshbenches
Oct 3 Lecture Debugging and Monitoring
Oct 3 Lecture Full and Parallel Case Differences in Simulation and Synthesis
Oct 6 Assignment HW 3 Due Fri Oct 13th
Oct 10 Lecture QUIZ
Oct 10 Lecture Slides Suggested Coding and Design Practices
Oct 17 Lecture Slides Details of Operations and Variables
Oct 18 Assignment HW 4 Preliminary Design Report Due 25th, Final Submission Oct 27.
Oct 26 Lecture Slides Synthesis and Loops, Single Assignment Code
Oct 24 Lecture Slides Synthesis and Loops
Nov 2 Lecture Slides FSM I
Nov Assignment HW 5 Preliminary Design Report Due Nov 10, Final Project Submission Nov 15.
Nov 7 Midterm Exam
Nov 9 Lecture Slides FSM II
Nov 20 Quiz topics related to procedural blocks and statemachines
Nov 21 Lecture continue state machines
Nov27 Assignment HW 6 Due Dec 4th
Nov 28 Lecture Timing, Testbenches and More Advanced Verilog
Dec 5 Assignment HW 7 Due Dec 12th NO LATE SUBMISSION
Dec 5 Lecture FPGA Developement
Dec 13 Wed Study Day
Dec 14 ThursFinal Exam Time: 1:00 - 3:00 Final Exam Schedule

Reading and References

Provided Materials

Vivado TCL

proj.tcl My first Vivado Non-Project Mode Tcl Script edited from Xilinx UG892

Test Bench example with File IO

Advanced Test Bench Examples

Soft Processor Cores

Example Pattern State Machine




Assigned: Thurdsay 2016/02/04
Due: Thursday 2016/02/11 24:00
HW 1
Submission instructions have been sent by email.
Submit the following:
1. A bitmap screenshoot (i.e. PNG file) of your Schematic
2. Your user constraints file (UCF)
3. The Verilog files for blocks in your schematic
If for some reason you cannot submit the schematic screenshot by tomorrow (Xilinx tools not accessible) please email it to me as soon as possible.


Assigned: 2016/02/25
Due: Monday 2016/03/04 at midnight
Assignment PDF
The TA's will distribute the points to the questions based on the difficulty and effort required to answer the questions. A distribution will be posted soon. Use the submission system to post to the hw3 folder. Late policy 20% for one day late and zero thereafter. Late homeworks should be posted to hw3_late.


Assigned: Fri 2017/10/06
Due: Fri 2017/10/13 at midnight
The assignment: HW3:Light the Candles
top.ucf just something for reference, read board manual and edit as needed
point distribution will be discussed in class
Repo: git clone USERNAME@gl.umbc.edu:/afs/umbc.edu/users/r/o/robucci/pub/cmpe415/submit/hw3/cmpe415_hw3_USERNAME


Assigned: 2010/09/22
Due Next Tues at midnight. 2010/09/18
You must show work with code and simulation results as appropriate.
You must provide testbenches to validate any any code written.
You must comment code.
You will only turn in a PDF
From Chapter 4 of the book:
7 a
7 b Repeat b four times as follows:
I) using behavioral code with if statements
II) using concurrent assign statement(s)
III) using primitives
IV) by creating a User Defined Primitive
16 a,f,g,h,i,k,l,n,o,p,r,s,t (read chapter and/or run code to find answers as needed)


Assigned: Wed morning 2010/03/10
Due Friday at midnight. 2010/03/25
For reference:
top.ucf for reference, read board manual and edit as needed


Assigned: Tues 2016/03/29
Due Wed 2016/04/06 before class: state-machine and top-level system diagram. (5 pts)
Due Friday 2016/04/08 before midnight: Project Submission.
Due Friday 2016/04/09 before midnight: Report which should include the final state machine and top-level system diagram.
(still seems a little glitchy sometimes, but usable)


Due Last Day of Semester Classes by midnight. 2016/05/10

HW6 OLD!!!

Assigned: Tuesday 2010/10/19
Due Next Tuesday before class. 2010/10/26
show all work, including code, in PDF

Final Project

'''Final Project''' Due The last Day of Classes..Dec 13. Check for updates. The final project will be graded based on successful completion and presentation of FPGA-based project. Students need to be able to identify the challenges of the design, document solution approaches, evaluate the success of the design, and make recommendations for further approaches for improvement. The grade will be based on the execution of the work, performance of the design on an FPGA, but also a presentation in written and/or oral form.
Groups of about 3 should have chosen a project. Each student must complete a portion of the coding that is equivalent to around a 1 1/2 week HW. This will be approved by the instructor. Each student will be responsible for creating test benches and reporting testing results to the team for their parts. The team will then work together to integrate the pieces, make corrections, and demonstrate the final operation. Each lab member must generate a comprehensive report including the project goals, the design approach, design decisions, description of design and reporting of testing of the all main parts (each student must report on all parts), issues encountered in integration and any corrections that needed to be made. More guidelines on the final report may be provided.
Nominal Grading unless provided otherwise:
50% Hardware demonstration successful. (common grade)
20% Personal coding: coding, commenting and documentation for your part, design and usability
10% Operation and Testing of your part (includes the testing, the reporting and evaluation of it)
10% Report evaluation of the following: the design, performance, use, and testing of other team members' parts. Be insightful and honest: describe what was good and bad. Was the interface good? Was enough testing done so that you were confident in the part? Did it work? Did it work as described or as you thought? etc...
10% Description of project, the pieces and interfaces, the process and experience especially including integration and interface challenges, and the successes and failures.